[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1

[Arthur Heymans (Code Review)]

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 )

Change subject: mb/ibm: Add IBM SBP1
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Patch Set 8: Code-Review+1

(4 comments)

File src/mainboard/ibm/sbp1/Kconfig:

https://review.coreboot.org/c/coreboot/+/73392/comment/1a3be99e_1443e8c0 
PS8, Line 14: select DEFAULT_X2APIC
Should be set at SOC level?

https://review.coreboot.org/c/coreboot/+/73392/comment/29834454_656c278e 
PS8, Line 40: config DEBUG_SMI
            : 	default y
Why?

File src/mainboard/ibm/sbp1/romstage.c:

https://review.coreboot.org/c/coreboot/+/73392/comment/4f661193_cd5f7f58 
PS8, Line 320: mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
Same at soc level.

https://review.coreboot.org/c/coreboot/+/73392/comment/cc01221e_a7fff26d 
PS8, Line 325: /* Set Attempt Fast Boot to enable. */
             : 	/* Enable - Portions of memory reference code will be skipped */
             : 	/* when possible to increase boot speed on warm boots.*/
             : 	/* Disable - Disables this feature. */
             : 	/* Auto - Sets it to the MRC default setting. */
             : 	mupd->FspmConfig.AttemptFastBoot = 0x1;
             : 
             : 	/* Set Attempt Fast Cold Boot to enable. */
             : 	/* Enable - Portions of memory reference code will be skipped */
             : 	/* when possible to increase boot speed on cold boots. */
             : 	/* Disable - Disables this feature. */
             : 	/* Auto - Sets it to the MRC default setting. */
             : 	mupd->FspmConfig.AttemptFastBootCold = 0x1;
Same settings are set at soc level.