Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
soc/skl/vr_config: fix GT Loadline for KBL-U/GT3
According to the documentation[1], the Loadline in the unslased GT VR domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006
Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35781/1
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index fc48558..de5ad2c 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -286,7 +286,7 @@ };
if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { - loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6); + loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); }
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... PS1, Line 289: loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); can you explain how to decode the referenced datasheet. I would use 6 here as it states that for GTX which is GT3.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
Patch Set 1:
(1 comment)
Patch Set 1:
Thanks for the review
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... PS1, Line 289: loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
can you explain how to decode the referenced datasheet. […]
If I understand correctly, then "2/6.0(GTx)" means Rgt = 2 mOhm, Rgtx = 6 mOhm for "U- 2 Core GT3+OPC".
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... PS1, Line 289: loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
If I understand correctly, then "2/6. […]
Ok, that makes sense. However how do you known that the VR_GT_SLICED is connected to Vcc_GTX and the UNSLICED is connected to Vcc_GT?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... PS1, Line 289: loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
Ok, that makes sense. […]
Yes of course. Therefore, loadline[VR_GT_UNSLICED (GT) ] = 2 mOhm and loadline[VR_GT_SLICED (GTX) ] = 6 mOhm.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35781/1/src/soc/intel/skylake/vr_co... PS1, Line 289: loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
Yes of course. Therefore, loadline[VR_GT_UNSLICED (GT) ] = 2 mOhm and […]
Great. As it's not documented there's lots of guessing involved, but it sounds reasonable.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35781 )
Change subject: soc/skl/vr_config: fix GT Loadline for KBL-U/GT3 ......................................................................
soc/skl/vr_config: fix GT Loadline for KBL-U/GT3
According to the documentation[1], the Loadline in the unslased GT VR domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006
Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/vr_config.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index fc48558..de5ad2c 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -286,7 +286,7 @@ };
if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { - loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6); + loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); }
-
Maxim Polyakov (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)