Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD: 1. tCKAVGmax 2. CAS Latencies supported (First Byte) 3. CAS Latencies supported (Second Byte) 4. CAS Latencies supported (Third Byte) 5. Minimum CAS Latency (tAAmin) 6. Read and Write Latency Set options 7. FTB for tAAmin 8. FTB for tCKAVGmax 9. FTB for tCKAVGmin
TEST=Able to build and boot with updated SPD.
Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/1
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d..e1d338e 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48079
to look at the new patch set (#2).
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD: 1. tCKAVGmax 2. CAS Latencies supported (First Byte) 3. CAS Latencies supported (Second Byte) 4. CAS Latencies supported (Third Byte) 5. Minimum CAS Latency (tAAmin) 6. Read and Write Latency Set options 7. FTB for tAAmin 8. FTB for tCKAVGmax 9. FTB for tCKAVGmin
TEST=Able to build and boot with updated SPD.
Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/2
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
Patch Set 2: Code-Review+1
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG@10 PS2, Line 10: 1. tCKAVGmax : 2. CAS Latencies supported (First Byte) : 3. CAS Latencies supported (Second Byte) : 4. CAS Latencies supported (Third Byte) : 5. Minimum CAS Latency (tAAmin) : 6. Read and Write Latency Set options : 7. FTB for tAAmin : 8. FTB for tCKAVGmax : 9. FTB for tCKAVGmin Instead of listing the low-level changes, how about explaining the high-level changes? For example:
1. Raise/Lower tCKAVGmax from X ns to Y ns
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG@10 PS2, Line 10: 1. tCKAVGmax : 2. CAS Latencies supported (First Byte) : 3. CAS Latencies supported (Second Byte) : 4. CAS Latencies supported (Third Byte) : 5. Minimum CAS Latency (tAAmin) : 6. Read and Write Latency Set options : 7. FTB for tAAmin : 8. FTB for tCKAVGmax : 9. FTB for tCKAVGmin
Instead of listing the low-level changes, how about explaining the high-level changes? For example: […]
Ack
Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48079
to look at the new patch set (#3).
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte)
TEST=Able to build and boot with updated SPD.
Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/3
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48079 )
Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ......................................................................
mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte)
TEST=Able to build and boot with updated SPD.
Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d..e1d338e 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00