Subrata Banik has uploaded this change for review.

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mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU

List of changes in SPD:
1. tCKAVGmax
2. CAS Latencies supported (First Byte)
3. CAS Latencies supported (Second Byte)
4. CAS Latencies supported (Third Byte)
5. Minimum CAS Latency (tAAmin)
6. Read and Write Latency Set options
7. FTB for tAAmin
8. FTB for tCKAVGmax
9. FTB for tCKAVGmin

TEST=Able to build and boot with updated SPD.

Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/1

diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
index 17f270d..e1d338e 100644
--- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
@@ -1,11 +1,11 @@
-23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
-48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60
+23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
+48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC
+00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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