Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)

[Angel Pons (Code Review)]

Attention is currently required from: Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Martin Roth, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 )

Change subject: src/intel/xeon_sp: add hardware error support (HEST)
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Patch Set 13:

(1 comment)

File src/soc/intel/xeon_sp/uncore.c:

https://review.coreboot.org/c/coreboot/+/52090/comment/5cfb3916_30c21bd5 
PS13, Line 292: 	/* Reserve memory for Enhanced error logging */
              : 	if (CONFIG(SOC_RAS_ELOG)) {
              : 		base_kb = cbmem_top_addr >> 10;
              : 		size_kb = CONFIG_ERROR_LOG_BUFFER_SIZE >> 10;
              : 		LOG_MEM_RESOURCE("elog_sts_blk", dev, index, base_kb, size_kb);
              : 		reserved_ram_resource(dev, index++, base_kb, size_kb);
              : 		elog_addr = cbmem_top_addr;
              : 		printk(BIOS_DEBUG, "%s elog_addr  = %llx size = %x\n",
              : 			__func__, elog_addr, CONFIG_ERROR_LOG_BUFFER_SIZE);
              : 	}
              :
> If I understand what you're doing correctly (trying to reserve CONFIG_ERROR_LOG_BUFFER_SIZE >> 10 by […]

Looks like the reserved region is placed right above CBMEM top. I'm worried that this may overlap with something else.