Attention is currently required from: Patrick Rudolph, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Andrey Petrov, Nathaniel L Desimone. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )
Change subject: soc/intel/*: Update microcode as specified for MP-init ......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/49899/comment/6319d2a5_9c1c3328 PS13, Line 70: PRMRR
For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immediately preceding it, therefore we have to use the MicrodeRegionBase UPD for ADL to have the FSP load the ucode patch a 2nd time.
For TGL, here are the snippets I can find in the BIOS core-uncore specs: ... For CML, #550049 says the following: ... I don't see anything in there w/r/t timing of 2nd load & SMM relocation.
Actually, I was asking for documentation about FSP not the hardware. The hardware is well documented. We know how to configure everything, probably even advanced things like SGX. But Intel explicitly wants to do things in FSP and that's what the MP init PPI was introduced for [1].
Now to actually allow that to work, I assume somebody needs to coordinate what is done in coreboot, what is done in FSP, and in what order. To be honest, I don't see how the pieces can fit together, so I'm asking.
So again, Subrata, Nate, please clarify how things fit together. For instance, how can we know at what point in coreboot we should do a second microcode update (especially considering the features that the MP init PPI was added for)?
[1] https://doc.coreboot.org/soc/intel/mp_init/mp_init.html
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Nico Huber (Code Review)