Change in coreboot[master]: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC

[Nick Vaccaro (Code Review)]

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54075 )

Change subject: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
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soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC

We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design.

BUG=b:184660529
TEST="emerge-volteer coreboot" compiles without error.

Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Signed-off-by: Nick Vaccaro 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/usb.h
3 files changed, 23 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index c011093..cc12da4 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -177,6 +177,8 @@
    uint16_t usb3_wake_enable_bitmap;
    /* PCH USB2 PHY Power Gating disable */
    uint8_t usb2_phy_sus_pg_disable;
+	/* Program OC pins for TCSS */
+	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];

/*
     * Acoustic Noise Mitigation
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 1f1f365..7c9ab88 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -269,6 +269,12 @@
    memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
    	sizeof(config->PcieRpClkReqDetect));

+	for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
+		if (config->tcss_ports[i].enable)
+			params->CpuUsb3OverCurrentPin[i] =
+					config->tcss_ports[i].ocpin;
+	}
+
    /* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
    if (dev) {
diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h
index 5dea4bf..dc66556 100644
--- a/src/soc/intel/tigerlake/include/soc/usb.h
+++ b/src/soc/intel/tigerlake/include/soc/usb.h
@@ -137,4 +137,19 @@
    .tx_downscale_amp = 0x00, \
 }

+struct tcss_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+};
+
+#define TCSS_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+}
+
+#define TCSS_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+}
+
 #endif