Change in coreboot[master]: soc/amd/cezanne: select HAVE_EM100_SUPPORT

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51711 )

Change subject: soc/amd/cezanne: select HAVE_EM100_SUPPORT
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soc/amd/cezanne: select HAVE_EM100_SUPPORT

This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.

Signed-off-by: Felix Held 
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/51711/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 7a69cc7..5e0e1a6 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -22,6 +22,7 @@
    select FSP_COMPRESS_FSP_S_LZMA
    select HAVE_ACPI_TABLES
    select HAVE_CF9_RESET
+	select HAVE_EM100_SUPPORT
    select HAVE_FSP_GOP
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE