Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov.
Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )
Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage ......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67669/comment/7751bb3f_827f24c1 PS1, Line 18:
The FSP reserved data contains the HOBs, among other things, so it should still be there in ramstage […]
Yeah, the FSP version info HOB is definitely there, it's just a question of how to get the right FSP version from it.
In my current build I have fsp_version = 0x0c028930, and the display_fsp_version_info_hob() output is: ``` [DEBUG] Display FSP Version Info HOB [DEBUG] Reference Code - CPU = c.0.89.30 [DEBUG] uCode Version = 0.0.0.c [DEBUG] TXT ACM version = ff.ff.ff.ffff [DEBUG] Reference Code - ME = c.0.89.30 [DEBUG] MEBx version = 0.0.0.0 [DEBUG] ME Firmware Version = Consumer SKU [DEBUG] Reference Code - PCH = c.0.89.30 [DEBUG] PCH-CRID Status = Disabled [DEBUG] PCH-CRID Original Value = ff.ff.ff.ffff [DEBUG] PCH-CRID New Value = ff.ff.ff.ffff [DEBUG] OPROM - RST - RAID = ff.ff.ff.ffff [DEBUG] PCH Hsio Version = 4.0.0.0 [DEBUG] Reference Code - SA - System Agent = c.0.89.30 [DEBUG] Reference Code - MRC = 0.0.4.49 [DEBUG] SA - PCIe Version = c.0.89.30 [DEBUG] SA-CRID Status = Disabled [DEBUG] SA-CRID Original Value = 0.0.0.0 [DEBUG] SA-CRID New Value = 0.0.0.0 [DEBUG] OPROM - VBIOS = ff.ff.ff.ffff [DEBUG] IO Manageability Engine FW Version = 23.0.8.0 [DEBUG] PHY Build Version = 0.0.0.fa5 [DEBUG] Thunderbolt(TM) FW Version = 0.0.0.0 [DEBUG] System Agent Manageability Engine FW Version = ff.ff.ff.ffff ```
So all the Reference Code versions almost match but not quite, and I'm not sure which one we'd want to use, or if they're always all the same. I'll find some docs or ask Intel.
Patchset:
PS1:
I think you've made an excellent point about the complexity of this situation, and whether it is wor […]
Ok, sounds good. I'll confirm with Intel whether checking the version before RAM init should work on pre-ADL platforms.
So let's put this patch on hold until the new flow is done. If we can get the single flow for all platforms working, then we can decide if it's worth making this change for 4 ms.
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Reka Norman (Code Review)