[L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email )

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Change subject: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms
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Patch Set 12: Code-Review+1

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81219/comment/8828818e_ce2712e5 :
PS12, Line 7: acorss
ac*ro*ss

File src/soc/intel/xeon_sp/ddr.c:

https://review.coreboot.org/c/coreboot/+/81219/comment/8f23f83c_9fb49186 :
PS12, Line 5: uint32_t get_ddr_voltage(uint8_t DdrVoltage)
Not as part of this change, because you just moved it around. But would
be nice to align with coreboot coding style.

https://review.coreboot.org/c/coreboot/+/81219/comment/246be347_e90600a4 :
PS12, Line 107: }
Also just moved around. But why is this a function? Such information belongs
into the devicetree.

Also, do we expect gaps or different amount of slots per channel? otherwise,
this could just be a `slot <= CONFIG_DIMM_MAX`.