Change in coreboot[master]: libpayload/arch/x86: support read cpu speed from msr

[JianfengX Zhou (Code Review)]

JianfengX Zhou has uploaded this change for review. ( https://review.coreboot.org/22943

Change subject: libpayload/arch/x86: support read cpu speed from msr
......................................................................

libpayload/arch/x86: support read cpu speed from msr

on icelake, "while (!(inb(0x61) & 0x20))" lead to dead loop,
can not boot normally.

when CONFIG_LP_GET_CPU_SPEED_FROM_MSR set to 1, read cpu speed from
msr platfrom information register.

Change-Id: I69da73ab479785c7b5d8add15705c1cd42925a75
Signed-off-by: zhouji3x 
---
M payloads/libpayload/arch/x86/timer.c
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22943/1

diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c
index bf0c30a..845876f 100644
--- a/payloads/libpayload/arch/x86/timer.c
+++ b/payloads/libpayload/arch/x86/timer.c
@@ -46,6 +46,21 @@
  *
  * @return The CPU speed in kHz.
  */
+#ifdef CONFIG_LP_GET_CPU_SPEED_FROM_MSR
+unsigned int get_cpu_speed(void)
+{
+	uint32_t info_lo;
+	uint32_t info_hi;
+	unsigned max_nb_ratio;
+
+	/* read MSR PLATFORM INFO */
+	asm volatile ("rdmsr" : "=a" (info_lo), "=d" (info_hi) : "c" (0xce));
+	max_nb_ratio = (info_lo >> 8) & 0xff;
+
+	cpu_khz = 100 * max_nb_ratio * 1000;
+	return cpu_khz;
+}
+#else
 unsigned int get_cpu_speed(void)
 {
    unsigned long long start, end;
@@ -76,3 +91,4 @@

return cpu_khz;
 }
+#endif