Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37764/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7bb533a..be4e26c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -74,22 +74,22 @@ default 0xfef00000
config DCACHE_RAM_SIZE - default 0x40000 + default 0x80000 help The size of the cache-as-ram region required during bootblock and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x20400 + default 0x30400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex - default 0x10000 + default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
Patch Set 1:
maulik, just check if TGL and JSL has same FSP temp ram requirement in integration guide else use dedicated Kconfig
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
Patch Set 1:
Patch Set 1:
maulik, just check if TGL and JSL has same FSP temp ram requirement in integration guide else use dedicated Kconfig
Yes Subrata..I have checked integration guide and TGL, JSL both has same temp ram and heap requirements
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
Patch Set 2: Code-Review+1
Wonkyu Kim has uploaded a new patch set (#3) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37764/3
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size ......................................................................
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764 Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7bb533a..be4e26c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -74,22 +74,22 @@ default 0xfef00000
config DCACHE_RAM_SIZE - default 0x40000 + default 0x80000 help The size of the cache-as-ram region required during bootblock and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x20400 + default 0x30400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex - default 0x10000 + default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know
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Maulik V Vaghela (Code Review) -
Patrick Georgi (Code Review)
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Rizwan Qureshi (Code Review)
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Subrata Banik (Code Review)
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Wonkyu Kim (Code Review)