[S] Change in coreboot[master]: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Arthur Heymans, Lean Sheng Tan.

Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Arthur Heymans, Lean Sheng Tan, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/69227

to look at the new patch set (#3).

Change subject: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
......................................................................

soc/intel: Use `PWRMBASE` over static `Index 0` for PMC

This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).

TEST=Able to build and boot Google, Rex to OS.

Without this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0

With this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik 
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
---
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/elkhartlake/pmc.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/meteorlake/pmc.c
M src/soc/intel/tigerlake/pmc.c
6 files changed, 35 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69227/3