Attention is currently required from: Michał Żygowski, Michał Kopeć, Angel Pons. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 )
Change subject: util/intelp2m: Add support for Alder Lake macro generation ......................................................................
Patch Set 4:
(1 comment)
File util/intelp2m/parser/parser.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/c8c985d9_79157905 PS4, Line 152: cnl.PlatformSpecific{}
snr.PlatformSpecific{} in the previous patch was right […]
I used your sample
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef CFG_GPIO_H #define CFG_GPIO_H
#include <gpio.h>
/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = {
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_I ------- */
/* GPP_I0 - GPIO */ /* DW0: 0x84000102, DW1: 0x00000000 */ /* DW0: (1 << 1) - IGNORED */ /* PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI), */ _PAD_CFG_STRUCT(GPP_I0, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
/* GPP_I1 - DDSP_HPD1 */ /* DW0: 0x84000500, DW1: 0x00000000 */ /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ /* PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), */ _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_I2 - DDSP_HPD2 */ /* DW0: 0x84000500, DW1: 0x00000000 */ /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ /* PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), */ _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_I3 - DDSP_HPD3 */ /* DW0: 0x84000502, DW1: 0x00000000 */ /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */ _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
* * * *