Attention is currently required from: Hung-Te Lin, Jarried Lin, Nancy Lin, Paul Menzel, Yu-Ping Wu.
Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email )
Change subject: soc/mediatek/mt8196: Add DDP driver ......................................................................
Patch Set 3:
(3 comments)
File src/soc/mediatek/common/display.c:
https://review.coreboot.org/c/coreboot/+/85950/comment/7a8cdb45_80adb8f1?usp... : PS2, Line 46: __weak int mtk_edp_enable(void)
This can't merged into mtk_edp_init. […]
Why do the past platforms (mt8195/mt8188) not follow this flow ?
File src/soc/mediatek/mt8196/ddp.c:
https://review.coreboot.org/c/coreboot/+/85950/comment/548af839_ac551f50?usp... : PS3, Line 267: setbits32(&exdma2_reg->rdma_burst_ctl, BIT(28)); : clrbits32(&exdma2_reg->rdma_burst_ctl, BIT(30)); : setbits32(&exdma2_reg->rdma_burst_ctl, BIT(31)); : setbits32(&exdma2_reg->dummy, BIT(2)); : setbits32(&exdma2_reg->dummy, BIT(3)); : setbits32(&exdma2_reg->datapath_con, BIT(0)); : setbits32(&exdma2_reg->datapath_con, BIT(24)); : setbits32(&exdma2_reg->datapath_con, BIT(25)); : clrbits32(&exdma2_reg->ovl_mout, BIT(0)); : setbits32(&exdma2_reg->ovl_mout, BIT(1)); can we use `clrsetbits32` for those settings ?
File src/soc/mediatek/mt8196/include/soc/addressmap.h:
https://review.coreboot.org/c/coreboot/+/85950/comment/657050b9_e6f0f9a7?usp... : PS3, Line 198: MMSYS_MUTEX_BASE = IO_PHYS + 0x22020000, move to line 190