Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ......................................................................
Patch Set 7:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/450ff552_4d22f2af PS7, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/d40d0582_a4a44328 PS7, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/5875e304_cb2f127c PS7, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/b94cae2f_1636e5b1 PS7, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/ea93bd71_8e8e0b63 PS7, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10); line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/0d030a60_35a51e12 PS7, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/7723062e_e9a44a25 PS7, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/098ec435_025f5edc PS7, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/9f977fd7_cfe01fcb PS7, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/449d33d3_1254616a PS7, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/39da7e42_b46a46e6 PS7, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/a214fd1e_9b68cc5f PS7, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/7841eb13_7a47583d PS7, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/27b009f9_086e012f PS7, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002): https://review.coreboot.org/c/coreboot/+/57886/comment/7af5584e_07a8f518 PS7, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); line over 96 characters