Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held.
15 comments:
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
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File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130002):
Patch Set #7, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
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