Change in coreboot[master]: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
2 files changed, 7 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38287/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 8602683..97f402e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3398,10 +3398,12 @@
 #define PCI_DEVICE_ID_INTEL_CML_ULT_2_2		0x9B71
 #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2		0x9B51
 #define PCI_DEVICE_ID_INTEL_CML_ULX		0x9B60
-#define PCI_DEVICE_ID_INTEL_CML_S		0x9B55
-#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2	0x9B53
-#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2	0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_S	0x9B55
+#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2	0x9B33
 #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2	0x9B43
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2	0x9B53
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_4	0x9B63
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_2	0x9B73
 #define PCI_DEVICE_ID_INTEL_CML_H		0x9B54
 #define PCI_DEVICE_ID_INTEL_CML_H_8_2		0x9B44
 #define PCI_DEVICE_ID_INTEL_TGL_ID_U		0x9A14
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 523c1a8..e12f748 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -83,6 +83,8 @@
    { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
    { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
    { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" },
    { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
    { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
 };

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 1:

what about adding into systemagent.c common code ?

[Gaggery Tsai (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Angel Pons, Balaji Manigandan, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38287

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/systemagent/systemagent.c
3 files changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38287/2

[Gaggery Tsai (Code Review)]

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 2:
> Patch Set 1:
>
> what about adding into systemagent.c common code ?

done

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 2: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
PS2, Line 3401: #define PCI_DEVICE_ID_INTEL_CML_S	0x9B55
This line lost a tab?

[Gaggery Tsai (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Angel Pons, Balaji Manigandan, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38287

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/systemagent/systemagent.c
3 files changed, 8 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38287/3

[Gaggery Tsai (Code Review)]

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
PS2, Line 3401: #define PCI_DEVICE_ID_INTEL_CML_S	0x9B55
> This line lost a tab?

Ack

[Gaggery Tsai (Code Review)]

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/38287/2/src/include/device/pci_ids.... 
PS2, Line 3401: #define PCI_DEVICE_ID_INTEL_CML_S	0x9B55
> Ack

Done

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 3: Code-Review+2

[Gaggery Tsai (Code Review)]

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 3:

Could someone help to submit this patch. I don't have permission. Thanks.

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/systemagent/systemagent.c
3 files changed, 8 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 6c3c298..59a3883 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3399,9 +3399,11 @@
 #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2		0x9B51
 #define PCI_DEVICE_ID_INTEL_CML_ULX		0x9B60
 #define PCI_DEVICE_ID_INTEL_CML_S		0x9B55
-#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2	0x9B53
-#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2	0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2	0x9B33
 #define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2	0x9B43
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2	0x9B53
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_4	0x9B63
+#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_2	0x9B73
 #define PCI_DEVICE_ID_INTEL_CML_H		0x9B54
 #define PCI_DEVICE_ID_INTEL_CML_H_4_2		0x9B64
 #define PCI_DEVICE_ID_INTEL_CML_H_8_2		0x9B44
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 19dce00..67dd452 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -83,6 +83,8 @@
    { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
    { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
    { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" },
+	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" },
    { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
    { PCI_DEVICE_ID_INTEL_CML_H_4_2, "CometLake-H (4+2)" },
    { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 0fab7d9..50e0524 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -391,6 +391,8 @@
    PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2,
    PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2,
    PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2,
+	PCI_DEVICE_ID_INTEL_CML_S_G0G1_4,
+	PCI_DEVICE_ID_INTEL_CML_S_G0G1_2,
    PCI_DEVICE_ID_INTEL_CML_H,
    PCI_DEVICE_ID_INTEL_CML_H_4_2,
    PCI_DEVICE_ID_INTEL_CML_H_8_2,

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38287 )

Change subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/157
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/156
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/155

Please note: This test is under development and might not be accurate at all!