Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48536 )
Change subject: nb/intel/sandybridge: Correct late DMI init sequence ......................................................................
nb/intel/sandybridge: Correct late DMI init sequence
Based on reference code, update the DMI ASPM setup steps.
Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 23 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48536/1
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4d87878..dc1be32 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -256,17 +256,15 @@ { const bool is_sandy = is_sandybridge();
- u32 reg32; + const u8 stepping = cpu_stepping();
- /* Clear error status bits */ - DMIBAR32(DMIUESTS) = 0xffffffff; - DMIBAR32(DMICESTS) = 0xffffffff; + u32 reg32;
/* Steps prior to DMI ASPM */ if (is_sandy) { reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22) | (1 << 20)); - reg32 |= (1 << 21); + reg32 &= ~(7 << 20); + reg32 |= (2 << 20); DMIBAR32(0x250) = reg32; }
@@ -274,12 +272,14 @@ reg32 |= (1 << 29); DMIBAR32(DMILLTC) = reg32;
- if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) { - reg32 = DMIBAR32(0x1f8); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; + if (is_sandy && stepping == SNB_STEP_C0) { + reg32 = DMIBAR32(0xbc8); + reg32 &= ~(0xfff << 7); + reg32 |= (0x7d3 << 7); + DMIBAR32(0xbc8) = reg32; + }
- } else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) { + if (!is_sandy || stepping >= SNB_STEP_D1) { reg32 = DMIBAR32(0x1f8); reg32 &= ~(1 << 26); reg32 |= (1 << 16); @@ -288,8 +288,20 @@ reg32 = DMIBAR32(0x1fc); reg32 |= (1 << 12) | (1 << 23); DMIBAR32(0x1fc) = reg32; + + } else if (stepping >= SNB_STEP_D0) { + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; }
+ /* Clear error status bits */ + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; + + if (!is_sandy) + DMIBAR32(0xc34) = 0xffffffff; + /* Enable ASPM on SNB link, should happen before PCH link */ if (is_sandy) { reg32 = DMIBAR32(0xd04);
Attention is currently required from: Angel Pons, Evgeny Zinoviev. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48536 )
Change subject: nb/intel/sandybridge: Correct late DMI init sequence ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48536 )
Change subject: nb/intel/sandybridge: Correct late DMI init sequence ......................................................................
nb/intel/sandybridge: Correct late DMI init sequence
Based on reference code, update the DMI ASPM setup steps.
Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 23 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4d87878..dc1be32 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -256,17 +256,15 @@ { const bool is_sandy = is_sandybridge();
- u32 reg32; + const u8 stepping = cpu_stepping();
- /* Clear error status bits */ - DMIBAR32(DMIUESTS) = 0xffffffff; - DMIBAR32(DMICESTS) = 0xffffffff; + u32 reg32;
/* Steps prior to DMI ASPM */ if (is_sandy) { reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22) | (1 << 20)); - reg32 |= (1 << 21); + reg32 &= ~(7 << 20); + reg32 |= (2 << 20); DMIBAR32(0x250) = reg32; }
@@ -274,12 +272,14 @@ reg32 |= (1 << 29); DMIBAR32(DMILLTC) = reg32;
- if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) { - reg32 = DMIBAR32(0x1f8); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; + if (is_sandy && stepping == SNB_STEP_C0) { + reg32 = DMIBAR32(0xbc8); + reg32 &= ~(0xfff << 7); + reg32 |= (0x7d3 << 7); + DMIBAR32(0xbc8) = reg32; + }
- } else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) { + if (!is_sandy || stepping >= SNB_STEP_D1) { reg32 = DMIBAR32(0x1f8); reg32 &= ~(1 << 26); reg32 |= (1 << 16); @@ -288,8 +288,20 @@ reg32 = DMIBAR32(0x1fc); reg32 |= (1 << 12) | (1 << 23); DMIBAR32(0x1fc) = reg32; + + } else if (stepping >= SNB_STEP_D0) { + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; }
+ /* Clear error status bits */ + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; + + if (!is_sandy) + DMIBAR32(0xc34) = 0xffffffff; + /* Enable ASPM on SNB link, should happen before PCH link */ if (is_sandy) { reg32 = DMIBAR32(0xd04);
-
Angel Pons (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)