Change in coreboot[master]: soc/intel/alderlake: Add support to enable UFS

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62662 )

Change subject: soc/intel/alderlake: Add support to enable UFS
......................................................................

soc/intel/alderlake: Add support to enable UFS

Signed-off-by: Meera Ravindranath 
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
---
M src/mainboard/intel/adlrvp/devicetree_n.cb
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/scs/Makefile.inc
A src/soc/intel/common/block/scs/ufs.c
5 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/62662/1

diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index f7da2d1..c2b74e3 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -280,6 +280,8 @@
    	device ref gspi0 on end
    	device ref p2sb on end
    	device ref emmc on end
+		device ref ish on end
+		device ref ufs on end
    	device ref hda on
    		chip drivers/intel/soundwire
    			device generic 0 on
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 09dc970..8021394 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -117,6 +117,7 @@
    	device pci 10.6 alias thc0 off end
    	device pci 10.7 alias thc1 off end
    	device pci 12.0 alias ish off end
+		device pci 12.7 alias ufs off end
    	device pci 12.6 alias gspi2 off end
    	device pci 13.0 alias gspi3 off end
    	device pci 14.0 alias xhci off
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b4e833b..cfdb5fb 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -604,12 +604,24 @@
 static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+
+	struct device *dev;
+
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
    /* eMMC Configuration */
    s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
    if (s_cfg->ScsEmmcEnabled)
    	s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode;
 #endif
+
+	/* UFS */
+	dev = pcidev_path_on_root(PCH_DEVFN_UFS);
+	if (!dev)
+		s_cfg->UfsEnable[1] = 0;
+	else {
+		s_cfg->UfsEnable[1] = dev->enabled;
+	}
+
    /* Enable Hybrid storage auto detection */
    s_cfg->HybridStorageMode = config->HybridStorageMode;
 }
diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc
index 0b77f5f..662ea04 100644
--- a/src/soc/intel/common/block/scs/Makefile.inc
+++ b/src/soc/intel/common/block/scs/Makefile.inc
@@ -2,4 +2,5 @@
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c
 endif
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += ufs.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c
diff --git a/src/soc/intel/common/block/scs/ufs.c b/src/soc/intel/common/block/scs/ufs.c
new file mode 100644
index 0000000..c51bf78
--- /dev/null
+++ b/src/soc/intel/common/block/scs/ufs.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <intelblocks/cfg.h>
+
+static struct device_operations dev_ops = {
+	.read_resources			= pci_dev_read_resources,
+	.set_resources			= pci_dev_set_resources,
+	.enable_resources		= pci_dev_enable_resources,
+	.ops_pci			= &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_ADP_UFS,
+	0
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+	.ops		= &dev_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids,
+};