[S] Change in coreboot[main]: soc/intel/pantherlake: Update power limits config

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85006?usp=email )

Change subject: soc/intel/pantherlake: Update power limits config
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soc/intel/pantherlake: Update power limits config

This updates power_limits_config for Panther Lake U and H.

Source:
  Intel PTL PDG 813278
  Intel PTL FSP Power limit profiles table

BUG=b:357011633
TEST=Build fatcat and boot with Panther Lake SoC and RVP.

Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/chipset.cb
2 files changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85006/1

diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 59aad4f..b59ce5e 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -65,9 +65,9 @@
 } cpuid_to_ptl[] = {
    { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
    { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W },
 };

/* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
index 4f6c8e04..f4c1b26 100644
--- a/src/soc/intel/pantherlake/chipset.cb
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -4,20 +4,20 @@

register "power_limits_config[PTL_U_1_CORE]" = "{
    	.tdp_pl1_override = 15,
-		.tdp_pl2_override = 54,
-		.tdp_pl4 = 142,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
    }"

register "power_limits_config[PTL_H_1_CORE]" = "{
    	.tdp_pl1_override = 25,
-		.tdp_pl2_override = 64,
-		.tdp_pl4 = 154,
+		.tdp_pl2_override = 95,
+		.tdp_pl4 = 239,
    }"

register "power_limits_config[PTL_H_2_CORE]" = "{
    	.tdp_pl1_override = 25,
-		.tdp_pl2_override = 80,
-		.tdp_pl4 = 240,
+		.tdp_pl2_override = 64,
+		.tdp_pl4 = 154,
    }"

# NOTE: if any variant wants to override this value, use the same format