Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

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Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39538/7/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.c:

https://review.coreboot.org/c/coreboot/+/39538/7/src/soc/intel/skylake/chip.... 
PS7, Line 135:  * Chip config parameters PcieRpAspm and PcieRpL1Substates use (UPD value + 1) because UPD values
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