Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63727 )
Change subject: [UNTESTED]soc/amd/picasso: Add support for 64bit builds ......................................................................
[UNTESTED]soc/amd/picasso: Add support for 64bit builds
Currently this still uses a static page table in ROM. It is unknown whether the hardware supports this. Futher patches will move the page tables to RAM.
Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 4 files changed, 18 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63727/1
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 7f50965..fef12f4 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -13,6 +13,7 @@
config SOC_AMD_COMMON_BLOCK_NONCAR bool + select HAVE_EXP_X86_64_SUPPORT help From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any more, since the RAM initialization is already done by the PSP when diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 5c16c29..503de3b 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -25,6 +25,10 @@ bootblock_pre_c_entry: post_code(0xa0)
+#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> +#endif + /* Clear .bss section */ cld xor %eax, %eax @@ -40,10 +44,17 @@ and $0xfffffff0, %esp sub $8, %esp
+#if ENV_X86_64 + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi +#else movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
post_code(0xa2)
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b005f9b..d6e9945 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -11,10 +11,8 @@ def_bool y select ACPI_SOC_NVS select ADD_FSP_BINARIES if USE_AMD_BLOBS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK && ARCH_ALL_STAGES_X86_32 + select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK && ARCH_ALL_STAGES_X86_64 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 8eef153..85cc511 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -136,7 +136,11 @@ # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_64),y) +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep -A1 LOAD | tr -d '\n' | awk '{print $$5}') +else PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +endif PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE
-
Arthur Heymans (Code Review)