Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 )
Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references ......................................................................
Patch Set 6:
(8 comments)
Patch Set 6:
(8 comments)
Patch Set 5:
Can you please organize the CLs this way:
- Copy the required source to JSL SoC.
- Move the Dedede & JSLRVP mainboards from TGL to JSL.
- Clean-up the TGL SoC tree and any mainboards using TGL.
That makes it better from the code-review standpoint.
Indeed. Furthermore, clean-up can be split in two changes:
- Remove all JSL code from TGL.
- Rename the "_tgl" files as necessary.
I had attempted copying the JSL specific code here: https://review.coreboot.org/c/coreboot/+/39775/1 Build failed due to SoC config conflict.
Dedede and JSLRVP mainboards are already subscribed to JSL SoC Kconfig.
The current plan is as below, does it help in review? I have updated the same in base CL.
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG@9 PS6, Line 9: jsl
JSL
Done
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG@9 PS6, Line 9: soc
SoC
Done
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG@9 PS6, Line 9: tgl
TGL
Done
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG@10 PS6, Line 10: Also removes
Add a subject: […]
Done
https://review.coreboot.org/c/coreboot/+/39774/6//COMMIT_MSG@10 PS6, Line 10: lake
Lake
Done
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/romstage.c:
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/google/voltee... PS6, Line 11: #include <soc/meminit_tgl.h>
I would not rely on indirect inclusion of `<baseboard/variants.h>`. Instead, update the include: […]
Agree, I tried this , but the build fails since variant.h from mainboard includes <soc/meminit.h> for using the data types defined in meminit.h. https://qa.coreboot.org/job/coreboot-gerrit/120270/testReport/junit/board/ch...
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/39774/6/src/mainboard/intel/tglrvp/... PS6, Line 20: #include <soc/meminit_tgl.h>
I would not rely on indirect inclusion of `<baseboard/variants.h>`. Instead, update the include: […]
Agree, I tried this , but the build fails since variant.h from mainboard includes <soc/meminit.h> for using the data types defined in meminit.h. https://qa.coreboot.org/job/coreboot-gerrit/120270/testReport/junit/board/ch...
https://review.coreboot.org/c/coreboot/+/39774/6/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs.asl:
PS6:
To make the diffstat easier to review, could we please rename the files in a separate change?
This should have shown as a rename of pci_irqs_tgl.asl. Shows it when I commit the changes locally:
# Changes to be committed: # modified: src/mainboard/google/volteer/romstage.c # modified: src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h # modified: src/mainboard/intel/tglrvp/romstage_fsp_params.c # modified: src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h # modified: src/soc/intel/tigerlake/Kconfig # modified: src/soc/intel/tigerlake/Makefile.inc # renamed: src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl -> src/soc/intel/tigerlake/acpi/pci_irqs.asl # deleted: src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl
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Aamir Bohra (Code Review)