Change in coreboot[master]: purism/librem_skl: Explicitely enable Intel SpeedStep Technology

[Youness Alaoui (Code Review)]

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/23684

Change subject: purism/librem_skl: Explicitely enable Intel SpeedStep Technology
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purism/librem_skl: Explicitely enable Intel SpeedStep Technology

Enabling Intel SpeedStep Technology ensures the ACPI tables contain
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.

The VMX feature was enabled by default by the FSP but a different
FSP might have it disabled, so this ensures that VMX is explicitely
enabled for the Librem machines. This option however doesn't seem
to work in the FSP since VMX doesn't actually get enabled but as
long as the features MSR remains unlocked, it's not critical.

Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui 
---
M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/23684/1

diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index e2e2ac0..9ce1d91 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -7,6 +7,9 @@
    register "deep_s5_enable_dc" = "0"
    register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

+	register "eist_enable" = "1"
+	register "VmxEnable" = "1"
+
    # GPE configuration
    # Note that GPE events called out in ASL code rely on this
    # route. i.e. If this route changes then the affected GPE