[M] Change in coreboot[main]: arch/riscv/romstage: Start from assembly

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68840?usp=email )

Change subject: arch/riscv/romstage: Start from assembly
......................................................................

arch/riscv/romstage: Start from assembly

Without this it would use the exception handler from the previous
stage.

Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68840
Reviewed-by: Maximilian Brune 
Tested-by: build bot (Jenkins) 
---
M src/arch/riscv/Makefile.inc
M src/arch/riscv/include/arch/header.ld
D src/arch/riscv/include/arch/stages.h
A src/arch/riscv/romstage.S
D src/arch/riscv/romstage.c
5 files changed, 39 insertions(+), 37 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maximilian Brune: Looks good to me, approved

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index e912120..bbd3959 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -96,7 +96,7 @@
 ################################################################################
 ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)

-romstage-y += romstage.c
+romstage-y += romstage.S

# Build the romstage

diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld
index ddb618c..bca852c 100644
--- a/src/arch/riscv/include/arch/header.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -8,8 +8,4 @@
    to_load PT_LOAD;
 }

-#if ENV_BOOTBLOCK || ENV_RAMSTAGE
 ENTRY(_start)
-#else
-ENTRY(stage_entry)
-#endif
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
deleted file mode 100644
index f9de2b5..0000000
--- a/src/arch/riscv/include/arch/stages.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ARCH_STAGES_H
-#define __ARCH_STAGES_H
-
-#include <main_decl.h>
-
-void stage_entry(int hart_id, void *fdt)
-	__attribute__((section(".text.stage_entry")));
-
-#endif
diff --git a/src/arch/riscv/romstage.S b/src/arch/riscv/romstage.S
new file mode 100644
index 0000000..bf85acb
--- /dev/null
+++ b/src/arch/riscv/romstage.S
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/encoding.h>
+#include <bits.h>
+#include <mcall.h>
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+	# initialize stack point for each hart
+	# and the stack must be page-aligned.
+	# 0xDEADBEEF used to check stack overflow
+	csrr a0, mhartid
+	la   t0, _stack
+	slli t1, a0, RISCV_PGSHIFT
+	add  t0, t0, t1
+	li   t1, 0xDEADBEEF
+	STORE t1, 0(t0)
+	li   t1, RISCV_PGSIZE - HLS_SIZE
+	add  sp, t0, t1
+
+	# initialize hart-local storage
+	csrr a0, mhartid
+	call hls_init
+
+	li   a0, CONFIG_RISCV_WORKING_HARTID
+	call smp_pause
+
+	# initialize entry of interrupt/exception
+	la   t0, trap_entry
+	csrw mtvec, t0
+
+	# clear any pending interrupts
+	csrwi mip, 0
+
+	# set up the mstatus register
+	call mstatus_init
+	tail main
diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c
deleted file mode 100644
index c7340b2..0000000
--- a/src/arch/riscv/romstage.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Entry points must be placed at the location the previous stage jumps
- * to (the lowest address in the stage image). This is done by giving
- * stage_entry() its own section in .text and placing it first in the
- * linker script.
- */
-
-#include <arch/stages.h>
-#include <arch/smp/smp.h>
-#include <mcall.h>
-
-void stage_entry(int hart_id, void *fdt)
-{
-	HLS()->hart_id = hart_id;
-	HLS()->fdt = fdt;
-	smp_pause(CONFIG_RISCV_WORKING_HARTID);
-
-	main();
-}