Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40555 )
Change subject: soc/intel/xeon_sp/cpx: Workaround FSP-M issues ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/40555/1/src/soc/intel/xeon_sp/cpx/r... File src/soc/intel/xeon_sp/cpx/romstage.c:
https://review.coreboot.org/c/coreboot/+/40555/1/src/soc/intel/xeon_sp/cpx/r... PS1, Line 22: 0xfe930000 Can we create a new config to use here instead of this value? MULTI_SOCKET_DCACHE_RAM_BASE, something like this ...
and add this to the cpx/Kconfig configuration as config MULTI_SOCKET_DCACHE_RAM_BASE
https://review.coreboot.org/c/coreboot/+/40555/1/src/soc/intel/xeon_sp/cpx/r... PS1, Line 23: 0x70000 same
-
Maxim Polyakov (Code Review)