[S] Change in coreboot[main]: soc/amd/cezanne: Disable I2S internal clock based on mainboard config

[Anand Vaikar (Code Review)]

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85865?usp=email )

Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................

soc/amd/cezanne: Disable I2S internal clock based on mainboard config

Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
2 files changed, 13 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/1

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index a8b7f22..2204b66 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -108,6 +108,8 @@
    	uint8_t tx_eq_post;
    	uint8_t tx_vboost_lvl;
    } edp_tuningset;
+	/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
+	bool   acp_i2s_use_external_48mhz_osc;
 };

#endif /* CEZANNE_CHIP_H */
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index b9f529d..39b1694 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -83,8 +83,17 @@
 static void fch_clk_output_48Mhz(void)
 {
    uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
-	/* Enable BP_X48M0 Clock Output */
-	ctrl |= BP_X48M0_OUTPUT_EN;
+	const struct soc_amd_cezanne_config *cfg;
+	cfg = config_of_soc();
+
+    /*Master clock is dsabled as the clock is given externally*/
+	/* If used external clock source for I2S, disable the internal clock output */
+	if (cfg->acp_i2s_use_external_48mhz_osc &&
+	cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM)
+		ctrl &= ~BP_X48M0_OUTPUT_EN;
+	else
+		ctrl |= BP_X48M0_OUTPUT_EN;
+
    /* Disable clock output in S0i3 */
    ctrl |= BP_X48M0_S0I3_DIS;
    misc_write32(MISC_CLK_CNTL0, ctrl);