Change in coreboot[master]: soc/intel/common/block: Add variable to correct pcie_rp indexing
Attention is currently required from: Nico Huber, Subrata Banik, Tim Wawrzynczak, EricR Lai. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61936 )
Change subject: soc/intel/common/block: Add variable to correct pcie_rp indexing ......................................................................
Patch Set 7:
(2 comments)
File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/61936/comment/c76364ad_1d58b78e PS3, Line 49: port_num = port_num - 1;
I'm pretty curious what exactly FSP does wrong. If somebody with the hard- […]
Hi Nico,
Here is the output you have requested. I had to put prints in FSP, so it's not in the exact same format. Also, before TBT PCIe init, if we read this root ports value is 0xFFFFFFFF.
During TBT PCIe enumeration values are as below: RootPortFn[0] LCAP= 0x2714C41 VID:466E8086 // 07.0 RootPortFn[1] LCAP= 0x3714C41 VID:463F8086 // 07.1 RootPortFn[2] LCAP= 0x4714C41 VID:462F8086 // 07.2
After FSP-S in coreboot: pcie_rp_original_idx:devid: 0x466e, LCAP :0x2724841, port_num: 2 pcie_rp_original_idx:devid: 0x463f, LCAP :0x3724841, port_num: 3 pcie_rp_original_idx:devid: 0x462f, LCAP :0x4724841, port_num: 4
File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/61936/comment/4dc5c2e2_979055df PS6, Line 56: return (port_num - 1 - group->port_num_start);
The new subtraction needs to happen before the `if`, otherwise the […]
Ack
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Maulik V Vaghela (Code Review)