Change in coreboot[master]: mb/google/brya/variants/primus, gimble: Update the FIVR configurations

[Casper Chang (Code Review)]

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56165 )

Change subject: mb/google/brya/variants/primus, gimble: Update the FIVR configurations
......................................................................

mb/google/brya/variants/primus, gimble: Update the FIVR configurations

This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.

Reference CB:55704

BUG=b:191897776, b:191213263

Signed-off-by: Casper Chang 
Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/primus/overridetree.cb
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56165/1

diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 914a8bf..e5bab8f 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -20,6 +20,13 @@
    end
 end
 chip soc/intel/alderlake
+
+	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+	
    register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
    register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
    register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 36d015d..8ada763 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -23,6 +23,12 @@

chip soc/intel/alderlake

+	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |