[M] Change in coreboot[main]: treewide: Prepare mode switch code for dynamically generated paging
Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79226?usp=email )
Change subject: treewide: Prepare mode switch code for dynamically generated paging ......................................................................
treewide: Prepare mode switch code for dynamically generated paging
Make the long mode entry code generic to prepare for dynamically generated page tables. entry64.inc now expects the caller to load the page tables' address into the EAX register.
The mode switch assembly now stashes the previous page table address to restore after the protected mode call is incomplete. Follow-up changes will program/use dynamically generated tables for the SIPI vector and SMM stub.
This is not a functional change.
Change-Id: I1ef7c8bee0c38395d5436f6479f11b3a4208f53e Signed-off-by: Benjamin Doron benjamin.doron@9elements.com --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/64bit/pt.S M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 11 files changed, 39 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/79226/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index e134717..cfdc2a7 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -162,6 +162,8 @@ subl $4, %esp
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax
#include <cpu/x86/64bit/entry64.inc>
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 76986ff..e8f256e 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -213,6 +213,8 @@ andl $0xfffffff0, %esp
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax
#include <cpu/x86/64bit/entry64.inc>
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index f7c023b..c541b1a 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -362,6 +362,9 @@ subl $4, %esp
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + #include <cpu/x86/64bit/entry64.inc>
movd %mm2, %rdi diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 0943e35..96ed468 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -77,6 +77,9 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp
+ /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + /* entry64.inc preserves ebx. */ #include <cpu/x86/64bit/entry64.inc>
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 7da68b4..7a01a4f 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -11,9 +11,6 @@
#if ENV_X86_64 .code32 -#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 -#error pagetables must be 4KiB aligned! -#endif
#include <cpu/x86/msr.h> #if defined(__RAMSTAGE__) @@ -22,11 +19,8 @@ #include <arch/rom_segs.h> #endif
- +/* Caller to provide address of page tables in eax */ setup_longmode: - /* Get page table address */ - movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax - /* load identity mapped page tables */ movl %eax, %cr3
diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index c27f540..7a4ab90 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -19,6 +19,10 @@ movl %gs, %eax push %rax
+ /* Backup cr3 to stack */ + movq %cr3, %rax + push %rax + /* Arguments to stack */ push %rdi push %rsi @@ -27,9 +31,9 @@
#include <cpu/x86/64bit/exit32.inc>
- movl -56(%ebp), %eax /* Argument count */ - movl -72(%ebp), %edx /* Argument 0 */ - movl -80(%ebp), %ecx /* Argument 1 */ + movl -64(%ebp), %eax /* Argument count */ + movl -80(%ebp), %edx /* Argument 0 */ + movl -88(%ebp), %ecx /* Argument 1 */
/* Align the stack */ andl $0xFFFFFFF0, %esp @@ -50,10 +54,13 @@ pushl %edx /* Argument 0 */
1: - movl -64(%ebp), %ebx /* Function to call */ + movl -72(%ebp), %ebx /* Function to call */ call *%ebx movl %eax, %ebx
+ /* Get page table address */ + movl -56(%ebp), %eax + /* Preserves ebx */ #include <cpu/x86/64bit/entry64.inc>
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index b105528..e990c71 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -7,6 +7,10 @@ * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty */
+#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 +#error pagetables must be 4KiB aligned! +#endif + .section .rodata #define _PRES (1ULL << 0) #define _RW (1ULL << 1) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 39973db..401e8e2 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -222,6 +222,9 @@ andl $0xfffffff0, %esp /* ensure stack alignment */
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + /* entry64.inc preserves ebx, esi, edi, ebp */ #include <cpu/x86/64bit/entry64.inc> movabs c_handler, %eax diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f97ab59..802dd92 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -194,6 +194,10 @@ */ #if ENV_X86_64 mov %ecx, %edi + + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + /* entry64.inc preserves ebx, esi, edi, ebp */ #include <cpu/x86/64bit/entry64.inc> mov %edi, %ecx diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index eb556fa..b06f0f5 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -27,6 +27,9 @@ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + #include <cpu/x86/64bit/entry64.inc> #endif
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 61cbe307..da84e7b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -279,6 +279,9 @@ andl $0xfffffff0, %esp
#if ENV_X86_64 + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + #include <cpu/x86/64bit/entry64.inc> movd %mm2, %rdi shlq $32, %rdi
-
Benjamin Doron (Code Review)