Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47567 )
Change subject: nb/intel/sandybridge: Program MR2 shadow register ......................................................................
nb/intel/sandybridge: Program MR2 shadow register
This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands.
Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47567/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4bdb82d..095d853 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -785,6 +785,22 @@ mr2reg |= (odt.rttwr / 60) << 9;
write_mrreg(ctrl, channel, rank, 2, mr2reg); + + /* Program MR2 shadow */ + u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); + + reg32 &= 3 << 14 | 3 << 6; + + reg32 |= mr2reg & ~(3 << 6); + + if (rank & 1) { + if (srt) + reg32 |= 1 << (rank / 2 + 6); + } else { + if (ctrl->rank_mirror[channel][rank]) + reg32 |= 1 << (rank / 2 + 14); + } + MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; }
static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel)
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47567
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Program MR2 shadow register ......................................................................
nb/intel/sandybridge: Program MR2 shadow register
This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47567/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47567 )
Change subject: nb/intel/sandybridge: Program MR2 shadow register ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47567 )
Change subject: nb/intel/sandybridge: Program MR2 shadow register ......................................................................
nb/intel/sandybridge: Program MR2 shadow register
This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47567 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 16 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d3b71d5..4d478a0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -775,6 +775,22 @@ mr2reg |= (odt.rttwr / 60) << 9;
write_mrreg(ctrl, channel, rank, 2, mr2reg); + + /* Program MR2 shadow */ + u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); + + reg32 &= 3 << 14 | 3 << 6; + + reg32 |= mr2reg & ~(3 << 6); + + if (rank & 1) { + if (srt) + reg32 |= 1 << (rank / 2 + 6); + } else { + if (ctrl->rank_mirror[channel][rank]) + reg32 |= 1 << (rank / 2 + 14); + } + MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; }
static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel)
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47567 )
Change subject: nb/intel/sandybridge: Program MR2 shadow register ......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/28111 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : FAIL : https://lava.9esec.io/r/28110 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/28109 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/28108 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/28107 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/28106
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Arthur Heymans (Code Review)