Change in coreboot[master]: nb/intel/sandybridge: Use loops on DMI register groups

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/early_dmi.c
1 file changed, 141 insertions(+), 137 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39631/1

diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c
index 99705bb..99ed2d6 100644
--- a/src/northbridge/intel/sandybridge/early_dmi.c
+++ b/src/northbridge/intel/sandybridge/early_dmi.c
@@ -20,179 +20,183 @@
 {
    int i;

-	DMIBAR32(0x0914) |= 0x80000000;
-	DMIBAR32(0x0934) |= 0x80000000;
+	DMIBAR32(0x0914) |= 1 << 31;
+	DMIBAR32(0x0934) |= 1 << 31;

for (i = 0; i < 4; i++) {
-		DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff;
-		DMIBAR32(0x0a04 + (i << 4)) |= 0x800;
+		DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000;
+		DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11);
    }
-	DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000;
+	DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30);

for (i = 0; i < 2; i++) {
-		DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff;
-		DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff;
+		DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000;
+		DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000;
    }

-	DMIBAR32(0x090c) &= 0xfe1fffff;
-	DMIBAR32(0x092c) &= 0xfe1fffff;

-	DMIBAR32(0x0904);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0904) = 0x7a1842ec;
-	DMIBAR32(0x090c);	// !!! = 0x00000208
-	DMIBAR32(0x090c) = 0x00000128;
-	DMIBAR32(0x0924);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0924) = 0x7a1842ec;
-	DMIBAR32(0x092c);	// !!! = 0x00000208
-	DMIBAR32(0x092c) = 0x00000128;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46139008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46139008;
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec;
+		DMIBAR32(0x090c + (i << 5));	// !!! = 0x00000208
+		DMIBAR32(0x090c + (i << 5)) = 0x00000128;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
+	}
+
    DMIBAR32(0x0c04);	// !!! = 0x2e680008
    DMIBAR32(0x0c04) = 0x2e680008;
-	DMIBAR32(0x0904);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0904) = 0x3a1842ec;
-	DMIBAR32(0x0924);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0924) = 0x3a1842ec;
-	DMIBAR32(0x0910);	// !!! = 0x00006300
-	DMIBAR32(0x0910) = 0x00004300;
-	DMIBAR32(0x0930);	// !!! = 0x00006300
-	DMIBAR32(0x0930) = 0x00004300;
-	DMIBAR32(0x0a00);	// !!! = 0x03042010
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042010
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042010
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042010
-	DMIBAR32(0x0a30) = 0x03042018;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0910 + (i << 5));	// !!! = 0x00006300
+		DMIBAR32(0x0910 + (i << 5)) = 0x00004300;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042010
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
    DMIBAR32(0x0c00);	// !!! = 0x29700c08
    DMIBAR32(0x0c00) = 0x29700c08;
-	DMIBAR32(0x0a04);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a04) = 0x0c0718f0;
-	DMIBAR32(0x0a14);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a14) = 0x0c0718f0;
-	DMIBAR32(0x0a24);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a24) = 0x0c0718f0;
-	DMIBAR32(0x0a34);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a34) = 0x0c0718f0;
-	DMIBAR32(0x0900);	// !!! = 0x50000000
-	DMIBAR32(0x0900) = 0x50000000;
-	DMIBAR32(0x0920);	// !!! = 0x50000000
-	DMIBAR32(0x0920) = 0x50000000;
-	DMIBAR32(0x0908);	// !!! = 0x51ffffff
-	DMIBAR32(0x0908) = 0x51ffffff;
-	DMIBAR32(0x0928);	// !!! = 0x51ffffff
-	DMIBAR32(0x0928) = 0x51ffffff;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03042018;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46139008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46139008;
-	DMIBAR32(0x0904);	// !!! = 0x3a1842ec
-	DMIBAR32(0x0904) = 0x3a1846ec;
-	DMIBAR32(0x0924);	// !!! = 0x3a1842ec
-	DMIBAR32(0x0924) = 0x3a1846ec;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03042018;
-	DMIBAR32(0x0908);	// !!! = 0x51ffffff
-	DMIBAR32(0x0908) = 0x51ffffff;
-	DMIBAR32(0x0928);	// !!! = 0x51ffffff
-	DMIBAR32(0x0928) = 0x51ffffff;
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a04 + (i << 4));	// !!! = 0x0c0708f0
+		DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0900 + (i << 5));	// !!! = 0x50000000
+		DMIBAR32(0x0900 + (i << 5)) = 0x50000000;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
+		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
+		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
+	}
+
    DMIBAR32(0x0c00);	// !!! = 0x29700c08
    DMIBAR32(0x0c00) = 0x29700c08;
+
    DMIBAR32(0x0c0c);	// !!! = 0x16063400
    DMIBAR32(0x0c0c) = 0x00063400;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46339008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46339008;
-	DMIBAR32(0x0700);	// !!! = 0x46339008
-	DMIBAR32(0x0700) = 0x45339008;
-	DMIBAR32(0x0720);	// !!! = 0x46339008
-	DMIBAR32(0x0720) = 0x45339008;
-	DMIBAR32(0x0700);	// !!! = 0x45339008
-	DMIBAR32(0x0700) = 0x453b9008;
-	DMIBAR32(0x0720);	// !!! = 0x45339008
-	DMIBAR32(0x0720) = 0x453b9008;
-	DMIBAR32(0x0700);	// !!! = 0x453b9008
-	DMIBAR32(0x0700) = 0x45bb9008;
-	DMIBAR32(0x0720);	// !!! = 0x453b9008
-	DMIBAR32(0x0720) = 0x45bb9008;
-	DMIBAR32(0x0700);	// !!! = 0x45bb9008
-	DMIBAR32(0x0700) = 0x45fb9008;
-	DMIBAR32(0x0720);	// !!! = 0x45bb9008
-	DMIBAR32(0x0720) = 0x45fb9008;
-	DMIBAR32(0x0914);	// !!! = 0x9021a080
-	DMIBAR32(0x0914) = 0x9021a280;
-	DMIBAR32(0x0934);	// !!! = 0x9021a080
-	DMIBAR32(0x0934) = 0x9021a280;
-	DMIBAR32(0x0914);	// !!! = 0x9021a280
-	DMIBAR32(0x0914) = 0x9821a280;
-	DMIBAR32(0x0934);	// !!! = 0x9021a280
-	DMIBAR32(0x0934) = 0x9821a280;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03242018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03242018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03242018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03242018;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46339008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46339008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45339008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45339008
+		DMIBAR32(0x0700 + (i << 5)) = 0x453b9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x453b9008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45bb9008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
+		DMIBAR32(0x0914 + (i << 5)) = 0x9021a280;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
+		DMIBAR32(0x0914 + (i << 5)) = 0x9821a280;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03242018;
+	}
+
    DMIBAR32(0x0258);	// !!! = 0x40000600
    DMIBAR32(0x0258) = 0x60000600;
-	DMIBAR32(0x0904);	// !!! = 0x3a1846ec
-	DMIBAR32(0x0904) = 0x2a1846ec;
-	DMIBAR32(0x0914);	// !!! = 0x9821a280
-	DMIBAR32(0x0914) = 0x98200280;
-	DMIBAR32(0x0924);	// !!! = 0x3a1846ec
-	DMIBAR32(0x0924) = 0x2a1846ec;
-	DMIBAR32(0x0934);	// !!! = 0x9821a280
-	DMIBAR32(0x0934) = 0x98200280;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1846ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec;
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9821a280
+		DMIBAR32(0x0914 + (i << 5)) = 0x98200280;
+	}
+
    DMIBAR32(0x022c);	// !!! = 0x00c26460
    DMIBAR32(0x022c) = 0x00c2403c;

early_pch_init_native_dmi_pre();

-	/* Write once settings. */
+	/* Write once settings */
    DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
-			    (2 << 0) |  // 5GT/s
-			    (2 << 12) | // L0s 128 ns to less than 256 ns
-			    (2 << 15);  // L1 2 us to less than 4 us
+			    (2 <<  0) |	// 5GT/s
+			    (2 << 12) |	// L0s 128 ns to less than 256 ns
+			    (2 << 15);	// L1 2 us to less than 4 us

-	DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
    while (DMIBAR16(DMILSTS) & TXTRN)
    	;

-	DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
    while (DMIBAR16(DMILSTS) & TXTRN)
    	;

-	const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
-	const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500;
+	const u8  w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
+	const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500;

printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
    /*
     * Virtual Channel resources must match settings in RCBA!
     *
-	 * Channel Vp and Vm are documented in
-	 * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel
-	 * Pentium Processor Family, and Desktop Intel Celeron Processor Family
-	 * Vol. 2"
+	 * Channel Vp and Vm are documented in:
+	 * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium
+	 *  Processor Family, and Desktop Intel Celeron Processor Family Vol. 2"
     */

/* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/1/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/1/src/northbridge/intel/sandy... 
PS1, Line 38: 	for (i = 0; i < 2; i++) {
braces {} are not necessary for single statement blocks

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39631

to look at the new patch set (#2).

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/early_dmi.c
1 file changed, 142 insertions(+), 137 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39631/2

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/2/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/2/src/northbridge/intel/sandy... 
PS2, Line 23: 	for (i = 0; i < 2; i++) {
braces {} are not necessary for single statement blocks

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39631

to look at the new patch set (#3).

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/early_dmi.c
1 file changed, 142 insertions(+), 137 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39631/3

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 23: 	for (i = 0; i < 2; i++) {
braces {} are not necessary for single statement blocks

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
For some reason, adding parentheses here changes the binary... That is Not A Good Sign...

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
> For some reason, adding parentheses here changes the binary... That is Not A Good Sign...

It shouldn't, and doesn't in my tests (GCC 9.2).

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
> It shouldn't, and doesn't in my tests (GCC 9.2).

It does when using GCC 8.3.0, which is weird.

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
> It does when using GCC 8.3.0, which is weird.

Re-tested with 8.3, still no difference. Talking about this:

-               DMIBAR32(0x0914 + (i << 5)) |= 1 << 31;
 +               DMIBAR32(0x0914 + (i << 5)) |= (1 << 31);

right?

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
> Re-tested with 8.3, still no difference. Talking about this: […]

Yes, I probably have a poisoned copy... I'll re-check.

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39631

to look at the new patch set (#4).

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/early_dmi.c
1 file changed, 142 insertions(+), 137 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39631/4

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/4/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/4/src/northbridge/intel/sandy... 
PS4, Line 23: 	for (i = 0; i < 2; i++) {
braces {} are not necessary for single statement blocks

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/early_dmi.c:

https://review.coreboot.org/c/coreboot/+/39631/3/src/northbridge/intel/sandy... 
PS3, Line 24: 1 << 31
> Yes, I probably have a poisoned copy... I'll re-check.

Looks like the real culprit is made out of flesh and bones, and is typing this very reply.

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 4: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG@10 
PS4, Line 10: "per-lane" or "per-bundle"
Wouldn't it be better to use these names (lane and bundle) as variables in the loops?

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 4: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG@10 
PS4, Line 10: "per-lane" or "per-bundle"
> Wouldn't it be better to use these names (lane and bundle) as variables in the loops?

Uh nvm that's done in the next commit.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39631/4//COMMIT_MSG@10 
PS4, Line 10: "per-lane" or "per-bundle"
> Uh nvm that's done in the next commit.

Yes, for some reason I ended up making two separate commits

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39631
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/northbridge/intel/sandybridge/early_dmi.c
1 file changed, 142 insertions(+), 137 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c
index 99705bb..dec371f 100644
--- a/src/northbridge/intel/sandybridge/early_dmi.c
+++ b/src/northbridge/intel/sandybridge/early_dmi.c
@@ -20,179 +20,184 @@
 {
    int i;

-	DMIBAR32(0x0914) |= 0x80000000;
-	DMIBAR32(0x0934) |= 0x80000000;
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0914 + (i << 5)) |= (1 << 31);
+	}

for (i = 0; i < 4; i++) {
-		DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff;
-		DMIBAR32(0x0a04 + (i << 4)) |= 0x800;
+		DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000;
+		DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11);
    }
-	DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000;
+	DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30);

for (i = 0; i < 2; i++) {
-		DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff;
-		DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff;
+		DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000;
+		DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000;
    }

-	DMIBAR32(0x090c) &= 0xfe1fffff;
-	DMIBAR32(0x092c) &= 0xfe1fffff;

-	DMIBAR32(0x0904);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0904) = 0x7a1842ec;
-	DMIBAR32(0x090c);	// !!! = 0x00000208
-	DMIBAR32(0x090c) = 0x00000128;
-	DMIBAR32(0x0924);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0924) = 0x7a1842ec;
-	DMIBAR32(0x092c);	// !!! = 0x00000208
-	DMIBAR32(0x092c) = 0x00000128;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46139008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46139008;
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec;
+		DMIBAR32(0x090c + (i << 5));	// !!! = 0x00000208
+		DMIBAR32(0x090c + (i << 5)) = 0x00000128;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
+	}
+
    DMIBAR32(0x0c04);	// !!! = 0x2e680008
    DMIBAR32(0x0c04) = 0x2e680008;
-	DMIBAR32(0x0904);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0904) = 0x3a1842ec;
-	DMIBAR32(0x0924);	// !!! = 0x7a1842ec
-	DMIBAR32(0x0924) = 0x3a1842ec;
-	DMIBAR32(0x0910);	// !!! = 0x00006300
-	DMIBAR32(0x0910) = 0x00004300;
-	DMIBAR32(0x0930);	// !!! = 0x00006300
-	DMIBAR32(0x0930) = 0x00004300;
-	DMIBAR32(0x0a00);	// !!! = 0x03042010
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042010
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042010
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042010
-	DMIBAR32(0x0a30) = 0x03042018;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x7a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0910 + (i << 5));	// !!! = 0x00006300
+		DMIBAR32(0x0910 + (i << 5)) = 0x00004300;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042010
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
    DMIBAR32(0x0c00);	// !!! = 0x29700c08
    DMIBAR32(0x0c00) = 0x29700c08;
-	DMIBAR32(0x0a04);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a04) = 0x0c0718f0;
-	DMIBAR32(0x0a14);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a14) = 0x0c0718f0;
-	DMIBAR32(0x0a24);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a24) = 0x0c0718f0;
-	DMIBAR32(0x0a34);	// !!! = 0x0c0708f0
-	DMIBAR32(0x0a34) = 0x0c0718f0;
-	DMIBAR32(0x0900);	// !!! = 0x50000000
-	DMIBAR32(0x0900) = 0x50000000;
-	DMIBAR32(0x0920);	// !!! = 0x50000000
-	DMIBAR32(0x0920) = 0x50000000;
-	DMIBAR32(0x0908);	// !!! = 0x51ffffff
-	DMIBAR32(0x0908) = 0x51ffffff;
-	DMIBAR32(0x0928);	// !!! = 0x51ffffff
-	DMIBAR32(0x0928) = 0x51ffffff;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03042018;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46139008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46139008;
-	DMIBAR32(0x0904);	// !!! = 0x3a1842ec
-	DMIBAR32(0x0904) = 0x3a1846ec;
-	DMIBAR32(0x0924);	// !!! = 0x3a1842ec
-	DMIBAR32(0x0924) = 0x3a1846ec;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03042018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03042018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03042018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03042018;
-	DMIBAR32(0x0908);	// !!! = 0x51ffffff
-	DMIBAR32(0x0908) = 0x51ffffff;
-	DMIBAR32(0x0928);	// !!! = 0x51ffffff
-	DMIBAR32(0x0928) = 0x51ffffff;
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a04 + (i << 4));	// !!! = 0x0c0708f0
+		DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0900 + (i << 5));	// !!! = 0x50000000
+		DMIBAR32(0x0900 + (i << 5)) = 0x50000000;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
+		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46139008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1842ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03042018;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0908 + (i << 5));	// !!! = 0x51ffffff
+		DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff;
+	}
+
    DMIBAR32(0x0c00);	// !!! = 0x29700c08
    DMIBAR32(0x0c00) = 0x29700c08;
+
    DMIBAR32(0x0c0c);	// !!! = 0x16063400
    DMIBAR32(0x0c0c) = 0x00063400;
-	DMIBAR32(0x0700);	// !!! = 0x46139008
-	DMIBAR32(0x0700) = 0x46339008;
-	DMIBAR32(0x0720);	// !!! = 0x46139008
-	DMIBAR32(0x0720) = 0x46339008;
-	DMIBAR32(0x0700);	// !!! = 0x46339008
-	DMIBAR32(0x0700) = 0x45339008;
-	DMIBAR32(0x0720);	// !!! = 0x46339008
-	DMIBAR32(0x0720) = 0x45339008;
-	DMIBAR32(0x0700);	// !!! = 0x45339008
-	DMIBAR32(0x0700) = 0x453b9008;
-	DMIBAR32(0x0720);	// !!! = 0x45339008
-	DMIBAR32(0x0720) = 0x453b9008;
-	DMIBAR32(0x0700);	// !!! = 0x453b9008
-	DMIBAR32(0x0700) = 0x45bb9008;
-	DMIBAR32(0x0720);	// !!! = 0x453b9008
-	DMIBAR32(0x0720) = 0x45bb9008;
-	DMIBAR32(0x0700);	// !!! = 0x45bb9008
-	DMIBAR32(0x0700) = 0x45fb9008;
-	DMIBAR32(0x0720);	// !!! = 0x45bb9008
-	DMIBAR32(0x0720) = 0x45fb9008;
-	DMIBAR32(0x0914);	// !!! = 0x9021a080
-	DMIBAR32(0x0914) = 0x9021a280;
-	DMIBAR32(0x0934);	// !!! = 0x9021a080
-	DMIBAR32(0x0934) = 0x9021a280;
-	DMIBAR32(0x0914);	// !!! = 0x9021a280
-	DMIBAR32(0x0914) = 0x9821a280;
-	DMIBAR32(0x0934);	// !!! = 0x9021a280
-	DMIBAR32(0x0934) = 0x9821a280;
-	DMIBAR32(0x0a00);	// !!! = 0x03042018
-	DMIBAR32(0x0a00) = 0x03242018;
-	DMIBAR32(0x0a10);	// !!! = 0x03042018
-	DMIBAR32(0x0a10) = 0x03242018;
-	DMIBAR32(0x0a20);	// !!! = 0x03042018
-	DMIBAR32(0x0a20) = 0x03242018;
-	DMIBAR32(0x0a30);	// !!! = 0x03042018
-	DMIBAR32(0x0a30) = 0x03242018;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46139008
+		DMIBAR32(0x0700 + (i << 5)) = 0x46339008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x46339008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45339008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45339008
+		DMIBAR32(0x0700 + (i << 5)) = 0x453b9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x453b9008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0700 + (i << 5));	// !!! = 0x45bb9008
+		DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
+		DMIBAR32(0x0914 + (i << 5)) = 0x9021a280;
+	}
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9021a080
+		DMIBAR32(0x0914 + (i << 5)) = 0x9821a280;
+	}
+
+	for (i = 0; i < 4; i++) {
+		DMIBAR32(0x0a00 + (i << 4));	// !!! = 0x03042018
+		DMIBAR32(0x0a00 + (i << 4)) = 0x03242018;
+	}
+
    DMIBAR32(0x0258);	// !!! = 0x40000600
    DMIBAR32(0x0258) = 0x60000600;
-	DMIBAR32(0x0904);	// !!! = 0x3a1846ec
-	DMIBAR32(0x0904) = 0x2a1846ec;
-	DMIBAR32(0x0914);	// !!! = 0x9821a280
-	DMIBAR32(0x0914) = 0x98200280;
-	DMIBAR32(0x0924);	// !!! = 0x3a1846ec
-	DMIBAR32(0x0924) = 0x2a1846ec;
-	DMIBAR32(0x0934);	// !!! = 0x9821a280
-	DMIBAR32(0x0934) = 0x98200280;
+
+	for (i = 0; i < 2; i++) {
+		DMIBAR32(0x0904 + (i << 5));	// !!! = 0x3a1846ec
+		DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec;
+		DMIBAR32(0x0914 + (i << 5));	// !!! = 0x9821a280
+		DMIBAR32(0x0914 + (i << 5)) = 0x98200280;
+	}
+
    DMIBAR32(0x022c);	// !!! = 0x00c26460
    DMIBAR32(0x022c) = 0x00c2403c;

early_pch_init_native_dmi_pre();

-	/* Write once settings. */
+	/* Write once settings */
    DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
-			    (2 << 0) |  // 5GT/s
-			    (2 << 12) | // L0s 128 ns to less than 256 ns
-			    (2 << 15);  // L1 2 us to less than 4 us
+			    (2 <<  0) |	// 5GT/s
+			    (2 << 12) |	// L0s 128 ns to less than 256 ns
+			    (2 << 15);	// L1 2 us to less than 4 us

-	DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
    while (DMIBAR16(DMILSTS) & TXTRN)
    	;

-	DMIBAR8(DMILCTL) |= 0x20; // Retrain link
+	DMIBAR8(DMILCTL) |= (1 << 5);	// Retrain link
    while (DMIBAR16(DMILSTS) & TXTRN)
    	;

-	const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
-	const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500;
+	const u8  w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
+	const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500;

printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
    /*
     * Virtual Channel resources must match settings in RCBA!
     *
-	 * Channel Vp and Vm are documented in
-	 * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel
-	 * Pentium Processor Family, and Desktop Intel Celeron Processor Family
-	 * Vol. 2"
+	 * Channel Vp and Vm are documented in:
+	 * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium
+	 *  Processor Family, and Desktop Intel Celeron Processor Family Vol. 2"
     */

/* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39631 )

Change subject: nb/intel/sandybridge: Use loops on DMI register groups
......................................................................

Patch Set 5:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1441
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1440
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1439

Please note: This test is under development and might not be accurate at all!