[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 7:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/a1aff95b_30651730?usp... :
PS7, Line 104: 0x40
> > I have been looking at the magic values of 0x20/0x40/0x70, but after digging through vendor BIOS,  […]

No, those values are from digging through p8z77-v vendor bios, module PcieLaneDxe, with Ghidra. Remember I said on my _le_plus there's only two options via one PCH GPIO.

And from that work, I see three possible configs: (8 bits MSB-LSB being GP57-50)
x111xx00 (x4)
x010xx00 (x1 with PCIEX1_2)
xxxxxx00 (?)

So, 0x70 and 0x20 are known to be correct. The third setting changing all of
GP54-GP56 to input means deferring to on board straps, that if I read my boardview right, is effectively x101xx00 or 0x50. Maybe try that and see what happens. This is sus because it diverts lane 2 away from PCIEX1_1 and effectively disables it, but since it will be going to PCIEX16_3 instead, it seems to allow a new config: PCIEX16_3 as x2. The only PCIe device I have on hand for testing is an Intel Optane nvme that seems to be x2 only itself, so...

Fixing _le_plus is for later, because I first need to develop some infrastructure first, seeing there are at least 3 boards in the family with the need.

And, that module being a DXE means all this is actually best done in ramstage, so expect some major rework here as well.