Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili... - coreboot-gerrit

5 Jan 2021


      Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )
Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Gerrit-Change-Number: 49104
Gerrit-PatchSet: 2
Gerrit-Owner: Tim Crawford tcrawford@system76.com
Gerrit-Reviewer: Jeremy Soller jeremy@system76.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-CC: Subrata Banik subrata.banik@intel.com
Gerrit-Comment-Date: Tue, 05 Jan 2021 17:26:26 +0000
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