Change in coreboot[master]: nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46681 )
Change subject: nb/intel/haswell/finalize.c: Align MC locking with Broadwell ......................................................................
nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down.
Tested on Asrock B85M Pro4, still boots and register is still locked.
Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46681/1
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1c83110..22f9862 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,6 +17,9 @@ pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
+ /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ @@ -26,9 +29,6 @@ MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0);
- /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; - /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46681
to look at the new patch set (#4).
Change subject: nb/intel/haswell/finalize.c: Align MC locking with Broadwell ......................................................................
nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down.
Tested on Asrock B85M Pro4, still boots and register is still locked.
Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46681/4
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46681 )
Change subject: nb/intel/haswell/finalize.c: Align MC locking with Broadwell ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46681 )
Change subject: nb/intel/haswell/finalize.c: Align MC locking with Broadwell ......................................................................
nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down.
Tested on Asrock B85M Pro4, still boots and register is still locked.
Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1c83110..22f9862 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,6 +17,9 @@ pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
+ /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ @@ -26,9 +29,6 @@ MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0);
- /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; - /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);
-
Angel Pons (Code Review) -
Nico Huber (Code Review)