[XS] Change in coreboot[main]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84368?usp=email )

Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
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Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.

This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.

BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.

Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/meteorlake/acpi/tcss.asl
1 file changed, 1 insertion(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jakub Czapiga: Looks good to me, approved

diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index dbe76f2..24d28f3 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -602,13 +602,7 @@
    	}

/* Request IOM for D3 cold entry sequence. */
-		/*
-		 * FIXME: Remove this workaround after resolving b/244082753
-		 *
-		 * Document #742990: TCCold exit flow may not complete when processor at package
-		 * C0. The implication is that the system may hang.
-		 */
-		// TD3C = 1
+		TD3C = 1
    }

PowerResource (D3C, 5, 0)