New patch to review for coreboot: 31cf9d3 AGESA binaryPI boards: Drop annoying commentary
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10283
-gerrit
commit 31cf9d3695078eb42d47f10b6dabbe3414205140 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat May 23 14:27:44 2015 +0300
AGESA binaryPI boards: Drop annoying commentary
Same comments were already removed for the latest board, the amd/lamar.
Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 10 +++++----- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 8 ++++---- src/mainboard/amd/olivehillplus/PlatformGnbPcie.c | 8 ++++---- src/mainboard/amd/parmer/PlatformGnbPcie.c | 14 +++++++------- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 12 ++++++------ src/mainboard/amd/south_station/PlatformGnbPcie.c | 8 ++++---- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 14 +++++++------- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 18 +++++++++--------- src/mainboard/amd/union_station/PlatformGnbPcie.c | 12 ++++++------ src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 8 ++++---- src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 8 ++++---- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 6 +++--- src/mainboard/biostar/am1ml/PlatformGnbPcie.c | 8 ++++---- src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c | 12 ++++++------ src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c | 8 ++++---- src/mainboard/hp/abm/PlatformGnbPcie.c | 8 ++++---- src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 14 +++++++------- src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c | 2 -- src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 14 +++++++------- src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c | 12 ++++++------ src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 12 ++++++------ src/mainboard/pcengines/apu1/PlatformGnbPcie.c | 10 +++++----- 22 files changed, 112 insertions(+), 114 deletions(-)
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 4e1db51..b84418d 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -53,13 +53,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -71,7 +71,7 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -80,13 +80,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) } diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 4ae20b6..220528b 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -29,7 +29,7 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -39,7 +39,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -49,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -69,7 +69,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c index 0bef0bd..7ebd1a5 100644 --- a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c @@ -23,7 +23,7 @@
const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -33,7 +33,7 @@ const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -43,7 +43,7 @@ const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -63,7 +63,7 @@ const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index cc25cb2..003fc01 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -75,48 +75,48 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index b851df6..7c4288e 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -51,19 +51,19 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, @@ -75,7 +75,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -84,14 +84,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeLvds, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index b36489d..e94b49b 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -53,20 +53,20 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -79,7 +79,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index d0370e9..dfa3057 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -75,48 +75,48 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 4, PCI Device Number 4, LAN */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index ba81724..bda85d7 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -28,43 +28,43 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // { -// DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array +// DESCRIPTOR_TERMINATE_LIST, // PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), // PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) // } @@ -73,13 +73,13 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) } diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index ad75c23..6a7f6f5 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -57,20 +57,20 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -83,7 +83,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -92,14 +92,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeHDMI, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeHDMI, Aux2, Hdp2} diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index 0a8dbba..140af92 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -57,13 +57,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -72,14 +72,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeDP, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index 6df1509..fa1cc65 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -29,7 +29,7 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -39,7 +39,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -49,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -69,7 +69,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index f2ab1cb..cbb5c9a 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -74,19 +74,19 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, diff --git a/src/mainboard/biostar/am1ml/PlatformGnbPcie.c b/src/mainboard/biostar/am1ml/PlatformGnbPcie.c index 6df1509..fa1cc65 100644 --- a/src/mainboard/biostar/am1ml/PlatformGnbPcie.c +++ b/src/mainboard/biostar/am1ml/PlatformGnbPcie.c @@ -29,7 +29,7 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -39,7 +39,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -49,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -69,7 +69,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c index 29323bd..637e8fa 100644 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c @@ -56,19 +56,19 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -80,7 +80,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -89,14 +89,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeDP, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} diff --git a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c index ac6d2a7..66bebc2 100644 --- a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c @@ -29,7 +29,7 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -39,7 +39,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -49,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -69,7 +69,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/hp/abm/PlatformGnbPcie.c b/src/mainboard/hp/abm/PlatformGnbPcie.c index 520007a..06010ce 100644 --- a/src/mainboard/hp/abm/PlatformGnbPcie.c +++ b/src/mainboard/hp/abm/PlatformGnbPcie.c @@ -30,7 +30,7 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = { { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, @@ -40,7 +40,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, @@ -50,7 +50,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, @@ -70,7 +70,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index b2403c1..5ea0a9b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -74,48 +74,48 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 7401481..79dce2f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -105,7 +105,6 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { - /* Descriptor flags. IMPORTANT! Terminate last element of array */ DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, @@ -132,7 +131,6 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* (DDI interface Lanes 12:15, DdB, ...) */ { - /* Descriptor flags. IMPORTANT! Terminate last element of array */ DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c index b2403c1..5ea0a9b 100644 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c +++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c @@ -74,48 +74,48 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */ { - 0, /* Descriptor flags */ + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { - DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index be105ba..44deb7d 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -57,19 +57,19 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) }, @@ -81,7 +81,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -90,14 +90,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeTravisDpToLvds, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeDP, Aux2, Hdp2} diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index ae40bc8..545388e 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -57,19 +57,19 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) }, @@ -81,7 +81,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -90,14 +90,14 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeAutoDetect, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) {ConnectorTypeAutoDetect, Aux2, Hdp2} diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcie.c b/src/mainboard/pcengines/apu1/PlatformGnbPcie.c index 079bc20..34740cb 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcie.c +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcie.c @@ -50,19 +50,19 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -74,7 +74,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } @@ -83,7 +83,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) {ConnectorTypeDP, Aux1, Hdp1}
-
Kyösti Mälkki