[S] Change in coreboot[main]: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78144?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug
......................................................................

mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plug

Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for
enable USB wake.

BUG=b:302230434
TEST=Verify USB-A device could wake up Boxy

Signed-off-by: Joey Peng 
Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144
Reviewed-by: Derek Huang 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/dedede/variants/boxy/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Derek Huang: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index c45d8f6..5c3e90c 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -82,6 +82,16 @@
    register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
    register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port C1

+	#Bitmap for Wake Enable on USB attach/detach
+	register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+					      USB_PORT_WAKE_ENABLE(2) | \
+					      USB_PORT_WAKE_ENABLE(3) | \
+					      USB_PORT_WAKE_ENABLE(4)"
+	register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+					      USB_PORT_WAKE_ENABLE(2) | \
+					      USB_PORT_WAKE_ENABLE(3) | \
+					      USB_PORT_WAKE_ENABLE(4)"
+
    device domain 0 on
    	device pci 04.0 on
    		chip drivers/intel/dptf