[M] Change in coreboot[main]: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78206?usp=email )

Change subject: [RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data
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[RFC] nb/intel/sandybridge: Pre-render constants in MRC pei_data

Portions of MRC raminit code only serves to enter fixed constants
into pei_data structure for MRC consumption.

Since the constants are concentrated in the front of the structure,
set up a truncated copy for compiler to render at build time.
Chipset code then uses it as a base to initialize the (in-CAR)
structure and fill in the remainder at runtime.

This trades 58 bytes of static data for 111 bytes of executable code,
for a presumed net saving of 53 bytes, yet romstage gained no actual
savings.

This is therefore submitted as an RFC.

Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f
Signed-off-by: Keith Hui 
---
M src/northbridge/intel/sandybridge/raminit_mrc.c
1 file changed, 40 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78206/1

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 69baf44..ee9e0e9 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -230,16 +230,47 @@
    u32 reserved[4];
 } __packed;

+/* This is a simple truncation of pei_data struct.
+   All members must match up to the cut. */
+struct pei_data_truncated
+{
+	uint32_t pei_version;
+	uint32_t mchbar;
+	uint32_t dmibar;
+	uint32_t epbar;
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t wdbbar;
+	uint32_t wdbsize;
+	uint32_t hpet_address;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t thermalbase;
+	uint32_t system_type;
+	uint32_t tseg_size;
+} __packed;
+
+const struct pei_data_truncated pd = {
+	.pei_version = PEI_VERSION,
+	.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
+	.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
+	.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
+	.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
+	.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
+	.wdbbar = 0x4000000,
+	.wdbsize = 0x1000,
+	.hpet_address = HPET_BASE_ADDRESS,
+	.rcba = (uintptr_t)DEFAULT_RCBA,
+	.pmbase = DEFAULT_PMBASE,
+	.gpiobase = DEFAULT_GPIOBASE,
+	.thermalbase = 0xfed08000,
+	.tseg_size = CONFIG_SMM_TSEG_SIZE,
+};
+
 static void northbridge_fill_pei_data(struct pei_data *pei_data)
 {
-	pei_data->mchbar       = CONFIG_FIXED_MCHBAR_MMIO_BASE;
-	pei_data->dmibar       = CONFIG_FIXED_DMIBAR_MMIO_BASE;
-	pei_data->epbar        = CONFIG_FIXED_EPBAR_MMIO_BASE;
-	pei_data->pciexbar     = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
-	pei_data->hpet_address = HPET_BASE_ADDRESS;
-	pei_data->thermalbase  = 0xfed08000;
    pei_data->system_type  = !(get_platform_type() == PLATFORM_MOBILE);
-	pei_data->tseg_size    = CONFIG_SMM_TSEG_SIZE;

if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) {
    	const struct device *dev = pcidev_on_root(1, 0);
@@ -253,12 +284,6 @@
 {
    const struct device *dev = pcidev_on_root(0x19, 0);

-	pei_data->smbusbar   = CONFIG_FIXED_SMBUS_IO_BASE;
-	pei_data->wdbbar     = 0x04000000;
-	pei_data->wdbsize    = 0x1000;
-	pei_data->rcba       = (uintptr_t)DEFAULT_RCBA;
-	pei_data->pmbase     = DEFAULT_PMBASE;
-	pei_data->gpiobase   = DEFAULT_GPIOBASE;
    pei_data->gbe_enable = dev && dev->enabled;
 }

@@ -332,7 +357,8 @@
    	enable_usb_bar();

memset(&pei_data, 0, sizeof(pei_data));
-	pei_data.pei_version = PEI_VERSION;
+	/* Initialize with pre-rendered values from a shortened copy */
+	memcpy(&pei_data, &pd, sizeof(pd));

northbridge_fill_pei_data(&pei_data);
    southbridge_fill_pei_data(&pei_data);