HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ......................................................................
nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1)
Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40370/1
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4353a9c..bb886d4 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2171,18 +2171,14 @@ MCHBAR32(C1DRC1) = reg32;
if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = MCHBAR16(UPMC1); + peg_bits &= ((1 << 5) | (1 << 0)); + if (i945_silicon_revision() > 1) MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + else /* Rev 0 and 1 */ MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } }
reg16 = MCHBAR16(UPMC2);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40370/3/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/c/coreboot/+/40370/3/src/northbridge/intel/i945/... PS3, Line 2174: /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ Why would you need to risk breaking things by changing this???
This is just wrong. The entire 16 bits of UPMC1 were updated before, and that is most likely intentional. Unless you have *reliable* documentation (not a mere datasheet where half the things are missing and the other half are reserved) that shows this is wrong, *and* that doing it this way fixes something without breaking anything else, then please don't change things.
In any case, you can still make things simpler without affecting the behavior:
u16 peg_bits = (1 << 4);
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */ peg_bits |= (1 << 5) | (1 << 0);
if (i945_silicon_revision() > 1) peg_bits |= (1 << 12);
MCHBAR16(UPMC1) = peg_bits;
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40370/3/src/northbridge/intel/i945/... File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/c/coreboot/+/40370/3/src/northbridge/intel/i945/... PS3, Line 2174: /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
Why would you need to risk breaking things by changing this??? […]
why will this break something???? We all know that there is no documentation .... and what we used to read registry on vendor (see util/inetl* ) and some reverse engineering. so I did that and found it written that way.
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ......................................................................
Abandoned
HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ......................................................................
Restored
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40370
to look at the new patch set (#4).
Change subject: nb/i945/raminit: Simplify if statement blocks ......................................................................
nb/i945/raminit: Simplify if statement blocks
Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/raminit.c 1 file changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40370/4
Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945/raminit: Simplify if statement blocks ......................................................................
Patch Set 5: Code-Review+1
Attention is currently required from: Angel Pons. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945/raminit: Simplify if statement blocks ......................................................................
Patch Set 5:
(1 comment)
File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/c/coreboot/+/40370/comment/44abaa1f_88c44766 PS3, Line 2174: /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
why will this break something???? […]
Ack
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40370 )
Change subject: nb/i945/raminit: Simplify if statement blocks ......................................................................
Abandoned