[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use BusLimit during PCI bus allocation - coreboot-gerrit

7 Aug 2023


      Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59396?usp=email )
Change subject: soc/intel/xeon_sp: Use BusLimit during PCI bus allocation
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Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5f698e3ddb73282d2351cde24091085cd02b9d97
Gerrit-Change-Number: 59396
Gerrit-PatchSet: 10
Gerrit-Owner: Arthur Heymans arthur.heymans@9elements.com
Gerrit-Reviewer: Anjaneya "Reddy" Chagam anjaneya.chagam@intel.com
Gerrit-Reviewer: Christian Walter christian.walter@9elements.com
Gerrit-Reviewer: Johnny Lin Johnny_Lin@wiwynn.com
Gerrit-Reviewer: Jonathan Zhang jon.zhixiong.zhang@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Chu Tim.Chu@quantatw.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Arthur Heymans arthur@aheymans.xyz
Gerrit-CC: Martin L Roth gaumless@gmail.com
Gerrit-CC: Paul Menzel paulepanter@mailbox.org
Gerrit-MessageType: abandon