Change in coreboot[master]: device/dram/ddr4.h: Align with DDR3 and DDR2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51898 )

Change subject: device/dram/ddr4.h: Align with DDR3 and DDR2
......................................................................

device/dram/ddr4.h: Align with DDR3 and DDR2

Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.

Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/device/dram/ddr4.c
M src/include/device/dram/ddr4.h
2 files changed, 24 insertions(+), 24 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
index e670b20..cc66dcc 100644
--- a/src/device/dram/ddr4.c
+++ b/src/device/dram/ddr4.c
@@ -163,7 +163,7 @@
  *		SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD
  *		SPD_STATUS_CRC_ERROR -- checksum mismatch
  */
-int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd)
+int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
 {
    u8 reg8;
    u8 bus_width, sdram_width;
@@ -261,7 +261,7 @@
 }

enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq,
-				  const dimm_attr *info)
+				  const struct dimm_attr_ddr4_st *info)
 {
    struct memory_info *mem_info;
    struct dimm_info *dimm;
@@ -298,16 +298,16 @@
    	dimm->mod_id = info->manufacturer_id;

switch (info->dimm_type) {
-		case SPD_DIMM_TYPE_SO_DIMM:
+		case SPD_DDR4_DIMM_TYPE_SO_DIMM:
    		dimm->mod_type = SPD_SODIMM;
    		break;
-		case SPD_DIMM_TYPE_72B_SO_RDIMM:
+		case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
    		dimm->mod_type = SPD_72B_SO_RDIMM;
    		break;
-		case SPD_DIMM_TYPE_UDIMM:
+		case SPD_DDR4_DIMM_TYPE_UDIMM:
    		dimm->mod_type = SPD_UDIMM;
    		break;
-		case SPD_DIMM_TYPE_RDIMM:
+		case SPD_DDR4_DIMM_TYPE_RDIMM:
    		dimm->mod_type = SPD_RDIMM;
    		break;
    	default:
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index eac8bf8..ee7a1ea 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -25,20 +25,20 @@
  * Module type (byte 3, bits 3:0) of SPD
  * This definition is specific to DDR4. DDR2/3 SPDs have a different structure.
  */
-enum spd_dimm_type {
-	SPD_DIMM_TYPE_EXTENDED			= 0x0,
-	SPD_DIMM_TYPE_RDIMM			= 0x1,
-	SPD_DIMM_TYPE_UDIMM			= 0x2,
-	SPD_DIMM_TYPE_SO_DIMM			= 0x3,
-	SPD_DIMM_TYPE_LRDIMM			= 0x4,
-	SPD_DIMM_TYPE_MINI_RDIMM		= 0x5,
-	SPD_DIMM_TYPE_MINI_UDIMM		= 0x6,
-	SPD_DIMM_TYPE_72B_SO_RDIMM		= 0x8,
-	SPD_DIMM_TYPE_72B_SO_UDIMM		= 0x9,
-	SPD_DIMM_TYPE_16B_SO_DIMM		= 0xc,
-	SPD_DIMM_TYPE_32B_SO_DIMM		= 0xd,
+enum spd_dimm_type_ddr4 {
+	SPD_DDR4_DIMM_TYPE_EXTENDED		= 0x0,
+	SPD_DDR4_DIMM_TYPE_RDIMM		= 0x1,
+	SPD_DDR4_DIMM_TYPE_UDIMM		= 0x2,
+	SPD_DDR4_DIMM_TYPE_SO_DIMM		= 0x3,
+	SPD_DDR4_DIMM_TYPE_LRDIMM		= 0x4,
+	SPD_DDR4_DIMM_TYPE_MINI_RDIMM		= 0x5,
+	SPD_DDR4_DIMM_TYPE_MINI_UDIMM		= 0x6,
+	SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM		= 0x8,
+	SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM		= 0x9,
+	SPD_DDR4_DIMM_TYPE_16B_SO_DIMM		= 0xc,
+	SPD_DDR4_DIMM_TYPE_32B_SO_DIMM		= 0xd,
    /* Masks to bits 3:0 to give the dimm type */
-	SPD_DIMM_TYPE_MASK			= 0xf
+	SPD_DDR4_DIMM_TYPE_MASK			= 0xf
 };

/**
@@ -46,9 +46,9 @@
  *
  * The characteristics of each DIMM, as presented by the SPD
  */
-typedef struct dimm_attr_st {
+struct dimm_attr_ddr4_st {
    enum spd_memory_type dram_type;
-	enum spd_dimm_type dimm_type;
+	enum spd_dimm_type_ddr4 dimm_type;
    char part_number[SPD_DDR4_PART_LEN + 1];
    u8 serial_number[4];
    u8 bus_width;
@@ -59,15 +59,15 @@
    u16 manufacturer_id;
    u16 vdd_voltage;
    bool ecc_extension;
-} dimm_attr;
+};

typedef u8 spd_raw_data[512];

-int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd);
+int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd);

enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
    			const u16 selected_freq,
-				const dimm_attr *info);
+				const struct dimm_attr_ddr4_st *info);

/**
  * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s