Change in coreboot[master]: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

TEST=Able to pass MRC training on DDR4/5 SKUs

Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/memory.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48078/1

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index c25b245..66ae55e 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -12,7 +12,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {40, 30, 33, 33, 30},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */

@@ -51,7 +51,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {50, 30, 30, 30, 27},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */

[Subrata Banik (Code Review)]

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48078

to look at the new patch set (#2).

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

TEST=Able to pass MRC training on DDR4/5 SKUs

Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/memory.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48078/2

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

Patch Set 2: Code-Review+1

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

Patch Set 2: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

Patch Set 2: Code-Review+2

So it wasn't working at all before?

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

Patch Set 2:
> Patch Set 2: Code-Review+2
>
> So it wasn't working at all before?

ERB has interleave support but CRB doesn't have it, hence ideally with ADL SoC, we should disable interleave for all SKUs.

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

TEST=Able to pass MRC training on DDR4/5 SKUs

Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) 
Reviewed-by: Sridhar Siricilla 
Reviewed-by: V Sowmya 
Reviewed-by: Angel Pons 
---
M src/mainboard/intel/adlrvp/memory.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index cab4ef9..5d374db 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -12,7 +12,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {40, 30, 33, 33, 30},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */

@@ -61,7 +61,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {50, 30, 30, 30, 27},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

Patch Set 5:
> Patch Set 2:
> > Patch Set 2: Code-Review+2
> >
> > So it wasn't working at all before?
>
> ERB has interleave support but CRB doesn't have it, hence ideally with ADL SoC, we should disable interleave for all SKUs.

Ack