Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

[Arthur Heymans (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )

Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
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Patch Set 1:

(1 comment)

File src/cpu/intel/socket_p/Kconfig:

https://review.coreboot.org/c/coreboot/+/52942/comment/c5c32718_84e6514c 
PS1, Line 16: 	default 0x10000
> CPU_INTEL_SOCKET_BGA956 and CPU_INTEL_SOCKET_M use 0x8000 here, and are never used with NO_CBFS_MCACHE. I'd simply drop `select NO_CBFS_MCACHE` from t400.

config.lenovo_t400_vboot_and_debug fails to build then :-/

I'm pretty sure cache won't be an issue but I can also strip down that config. Any thoughts? Obviously t400 should not miss out on cbfs_mcache because of a probably not booting debug buildtest.