Change in coreboot[master]: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support ......................................................................
vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support
Experimental XMP support which will be tested ASAP on f15tn and f16kb. Added using the datasheets from https://github.com/mikebdp2/ddr3spd
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 264 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/1
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..5291a9c 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -46,6 +46,10 @@ source "src/vendorcode/amd/pi/Kconfig" endif
+if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + config AGESA_EXTRA_TIMESTAMPS bool "Add instrumentation for AGESA calls" default n diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..dcfa722 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,44 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist at ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists at ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists at ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..bd4c372 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +106,75 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..058eead 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -102,18 +105,75 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..da9d09f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +106,87 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +194,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38
-#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *-----------------------------
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support ......................................................................
Patch Set 1:
Later I could try to take the not-used-yet XMP-only fields into account. Examples:
1) Add a check for XMP profiles presence, and fallback from XMP_2 --> XMP_1 --> JEDEC if XMP_2 or XMP_1 does not exist. This check is simple - see "XMP_PROFILES 178" at https://github.com/mikebdp2/ddr3spd/blob/master/ddr3spd.c - but inserting it to AGESA could be tricky.
2) There is "XMP_1_CMD_RATE 208"/"XMP_2_CMD_RATE 243". Many XMP profiles have 1T or 2T rate (mine are 2T), and - if I understood the AGESA noodles correctly - SlowMode aka SlowAccessMode (for 2T CMD mode instead of 1T) is already enabled via ./Include/PlatformMemoryConfiguration.h , so they should work; but some profiles could need a 3T.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@7 PS1, Line 7: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support Please make that a statement by adding a verb (in imperative mood):
Add XMP memory profiles support
Support XMP memory profiles
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@7 PS1, Line 7: vendorcode vc
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@10 PS1, Line 10: Added using the datasheets from https://github.com/mikebdp2/ddr3spd Please list the name and section for one family.
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... File src/vendorcode/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 22: Please remove the white space.
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 25: a coreboot's fork Just *coreboot’s fork*?
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 35: at on?
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h:
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/f1... PS1, Line 167: bit bits?
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#2).
Change subject: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support ......................................................................
vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support
Experimental XMP support which will be tested ASAP on f15tn and f16kb. Added using the datasheets from https://github.com/mikebdp2/ddr3spd
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 246 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/2
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#3).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/3
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@7 PS1, Line 7: vendorcode
vc
Done
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@7 PS1, Line 7: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support
Please make that a statement by adding a verb (in imperative mood): […]
Done
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@10 PS1, Line 10: Added using the datasheets from https://github.com/mikebdp2/ddr3spd
Please list the name and section for one family.
Done?
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... File src/vendorcode/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 22:
Please remove the white space.
Done
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 25: a coreboot's fork
Just *coreboot’s fork*?
Done ;)
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/Kc... PS1, Line 35: at
on?
Done
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h:
https://review.coreboot.org/c/coreboot/+/40291/1/src/vendorcode/amd/agesa/f1... PS1, Line 167: bit
bits?
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@10 PS1, Line 10: Added using the datasheets from https://github.com/mikebdp2/ddr3spd I meant something like:
see BKGD section …, page … for the more information
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#4).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/4
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 4:
(1 comment)
Tested on f16 ASUS AM1I-A with one BLT8G3D1869DT1TX0 stick plugged into DIMM_A2 slot, DIMM_A1 left unoccupied.
See this shortened IDS Tracing log at https://pastebin.com/9nECWnF3 : look like I'm almost there, lots of steps passed successfully, but a board got stuck at "Step 16, Wait for rom firmware authentication vector" - infinite repeating lines after that. Any ideas?
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40291/1//COMMIT_MSG@10 PS1, Line 10: Added using the datasheets from https://github.com/mikebdp2/ddr3spd
I meant something like: […]
Done
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#6).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 250 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/6
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#7).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 358 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/7
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#8).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 8 files changed, 487 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/8
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#9).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 8 files changed, 487 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/9
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#10).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 11 files changed, 490 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/10
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#11).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/mainboard/asus/am1i-a/buildOpts.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 15 files changed, 510 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/11
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 11:
Cause of my earlier problem: although the SPD Buffer is 256 bytes in AGESA's vendorcode, the smbus_readSpd function only read the first 128 bytes: so at SPD Buffer's XMP profile offset there was a bunch of 00 instead of real values. I didn't notice it at first, but this instantly became clear after a full print of read SPD Buffer. After I changed that to 256, now the XMP 1 "1866MHz" profile is giving me 1600MHz speed - which of course is better than turtle 1333MHz, but now I need to figure out: what else is blocking a 1866MHz? Maybe a northbridge frequency? Also, started working on a custom SPD values set up as you see, although it's a lower priority.
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#12).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 14 files changed, 507 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/12
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#13).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 14 files changed, 507 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/13
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 13:
Patch Set 11:
Cause of my earlier problem: although the SPD Buffer is 256 bytes in AGESA's vendorcode, the smbus_readSpd function only read the first 128 bytes: so at SPD Buffer's XMP profile offset there was a bunch of 00 instead of real values. I didn't notice it at first, but this instantly became clear after a full print of read SPD Buffer. After I changed that to 256, now the XMP 1 "1866MHz" profile is giving me 1600MHz speed - which of course is better than turtle 1333MHz, but now I need to figure out: what else is blocking a 1866MHz? Maybe a northbridge frequency? Also, started working on a custom SPD values set up as you see, although it's a lower priority.
It seems that f16kb Athlon 5370 's Kabini memory controller supports up to 1600MHz max unless you would overclock the northbridge (see the MEMCLK / NCLK / NBCOF comments). For that, it seems that you need to disable a check for northbridge read-only bit fields stating that 1600MHz is max freq supported and raise the base clock from 100MHz to 120MHz (120*8 = 960 > 933). Also may need to overclock the graphics memory controller as well (./src/vendorcode/amd/agesa/f16kb/Proc/GNB) to keep up with the RAM speeds.
All this is tricky to do: although there are defines like EXTERNAL_CLOCK_100MHZ and GFX_REFCLK, it seems that in many places which are supposed to use this CLK value, it is simply hardcoded as "100 *" or "* 100" - and sometimes hard to figure out, which 100 should be changed to 120 and which shouldn't. So for this moment I'm fine with 1600MHz at f16kb AM1I-A, considering the timings also got lower: 1600MHz 8-8-9-23 instead of 1866MHz 9-9-9-27 (or 9-9-10-27: for some reason tRP is always trained one point higher while the rest of tCL-tRCD-tRP-tRAS are the same as RAM specification. May have to do with SlowMode? see SpdIndexes at mtspd3.c to find out)
For those who would like to continue overclocking AM1I-A, take a look at f16kb-only feature AMP (AMD Memory Profiles) which may affect the northbridge performance / voltages, maybe enabling it will assist in overclocking. Meanwhile I'll try to get ASUS A88XM-E with A10-6700 working: yesterday when I tried to enable "XMP 1" 1866MHz profile on it, maybe it trained to 1866MHz as requested (since f15tn A10-6700 's memory controller really supports 1866MHz without overclocking) but I got a weird exception which prevented the successful booting:
... PCI: 00:18.5 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1417 ms
APIC 00: ** Enter AmdInitMid [00020005] Timestamp - calling AmdInitMid: 24619341360 CPU Index 0 - APIC 16 Unexpected Exception:0 @ 10:1febbe1d - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00017318 ebx: 10000660 ecx: 00000004 edx: 00000000 edi: 00000000 esi: 0000014d ebp: 00000016 esp: 1fedec70
0x1febbdd8: c7 5e ff 33 8a 44 24 4b 0x1febbde0: 83 e0 1f 50 e8 b0 13 00 0x1febbde8: 00 83 c4 10 89 c6 83 ec 0x1febbdf0: 0c ff 33 6a 00 8d 44 24 0x1febbdf8: 38 50 68 70 01 00 00 6a 0x1febbe00: 0f e8 b3 26 00 00 83 c4 0x1febbe08: 14 80 7c 24 33 00 ff 33 0x1febbe10: 0f 48 f7 e8 c3 13 00 00 0x1febbe18: 6b c0 64 31 d2 f7 f7 89 0x1febbe20: 44 24 14 5f ff 33 e8 b0 0x1febbe28: 13 00 00 6b c0 64 31 d2 0x1febbe30: f7 f6 89 c5 58 ff 33 6a 0x1febbe38: 00 8d 44 24 24 50 68 74 0x1febbe40: 27 00 00 6a 12 e8 6f 26 0x1febbe48: 00 00 83 c4 14 ff 33 6a 0x1febbe50: 00 8d 44 24 28 50 68 78
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#14).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 12 files changed, 491 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/14
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#15).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 15 files changed, 580 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/15
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#16).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 15 files changed, 580 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/16
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#17).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 15 files changed, 583 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/17
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 17:
Patch Set 13:
Meanwhile I'll try to get ASUS A88XM-E with A10-6700 working: yesterday when I tried to enable "XMP 1" 1866MHz profile on it, maybe it trained to 1866MHz as requested (since f15tn A10-6700 's memory controller really supports 1866MHz without overclocking) but I got a weird exception which prevented the successful booting:
... PCI: 00:18.5 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1417 ms
APIC 00: ** Enter AmdInitMid [00020005] Timestamp - calling AmdInitMid: 24619341360 CPU Index 0 - APIC 16 Unexpected Exception:0 @ 10:1febbe1d - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00017318 ebx: 10000660 ecx: 00000004 edx: 00000000 edi: 00000000 esi: 0000014d ebp: 00000016 esp: 1fedec70
0x1febbdd8: c7 5e ff 33 8a 44 24 4b 0x1febbde0: 83 e0 1f 50 e8 b0 13 00 0x1febbde8: 00 83 c4 10 89 c6 83 ec 0x1febbdf0: 0c ff 33 6a 00 8d 44 24 0x1febbdf8: 38 50 68 70 01 00 00 6a 0x1febbe00: 0f e8 b3 26 00 00 83 c4 0x1febbe08: 14 80 7c 24 33 00 ff 33 0x1febbe10: 0f 48 f7 e8 c3 13 00 00 0x1febbe18: 6b c0 64 31 d2 f7 f7 89 0x1febbe20: 44 24 14 5f ff 33 e8 b0 0x1febbe28: 13 00 00 6b c0 64 31 d2 0x1febbe30: f7 f6 89 c5 58 ff 33 6a 0x1febbe38: 00 8d 44 24 24 50 68 74 0x1febbe40: 27 00 00 6a 12 e8 6f 26 0x1febbe48: 00 00 83 c4 14 ff 33 6a 0x1febbe50: 00 8d 44 24 28 50 68 78
It's related to issue in thread https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html - ariphmetic (division?) error at ./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c - line 334 - which happens only if RAM frequency is 1866MHz! When I forced a 1600MHz by changing "#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY" to DDR1600_FREQUENCY at ./src/mainboard/asus/a88xm-e/buildOpts.c , a board booted fine. So need to investigate if it's something as simple as changing i.e. memps0_freq from 0 to 1, or everything is tied to the hardcoded values and hardly fixable. At least the 1600MHz timings are good enough in case I would fail.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 17:
Patch Set 17:
[…]
It's related to issue in thread https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html - ariphmetic (division?) error at ./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c - line 334 - which happens only if RAM frequency is 1866MHz! When I forced a 1600MHz by changing "#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY" to DDR1600_FREQUENCY at ./src/mainboard/asus/a88xm-e/buildOpts.c , a board booted fine. So need to investigate if it's something as simple as changing i.e. memps0_freq from 0 to 1, or everything is tied to the hardcoded values and hardly fixable. At least the 1600MHz timings are good enough in case I would fail.
Can you add debug print statements to the if statement
if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface)
to see what branch is chosen, and what values it is set to?
In AMD Family 16h (from 2013 instead 2012) the code seems to have been moved to `src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c`.
Hello build bot (Jenkins), Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40291
to look at the new patch set (#18).
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Experimental XMP support which will be tested ASAP on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs)
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 16 files changed, 584 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/18
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 18:
Patch Set 17:
Can you add debug print statements to the if statement
if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface)to see what branch is chosen, and what values it is set to?
In AMD Family 16h (from 2013 instead 2012) the code seems to have been moved to `src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c`.
Paul, thank you for advice! memps0_freq got 0 value from a function GfxLibExtractDramFrequency, which returned zero because there wasn't a "933" entry at GfxMemClockFrequencyDefinitionTable. After I inserted 933 to it, now a board successfully boots as 1866MHz 9-9-10-27 (with AGESA, CL-tRCD-tRP-tRAS , tRP is always 1 digit higher than CL/tRCD for some reason) as told by memtest86+ 5.01, and already 2 successful passes ;-) (using memtest86+ 4.37 for testing because 5.01 always gives me lots of false positives at a certain range, no matter what board or RAM).
f14 doesn't have this table, and f16kb table already has a 933 value in its' table at src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c , so it could also run at 1866MHz but only with overclocking a memory controller / northbridge, which isn't easy to do because of hardcoded base clock at many places
So happy with results :) Should I move a change to "Gfx table", and maybe also the northbridge's "128 -> 256 bytes" SPD change which is outside of ./src/vendorcode/, to the separate changes?
Mike Banon has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Abandoned
Superseded by CB:40484 , CB:40485 , CB:40488 , CB:40489 , CB:40490 .
Mike Banon has restored this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Restored
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Patch Set 18:
By the way, I found out why the timings are always 9-9-10-24 or 9-9-10-27 instead of 9-9-9-X with AMD: (CL-tRCD-tRP-tRAS) - tRP gets set 1 point higher by AGESA because of CPU errata 638.
Mike Banon has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ......................................................................
Abandoned
Superseded by CB:40484 , CB:40485 , CB:40488 , CB:40489 , CB:40490 .
-
Mike Banon (Code Review) -
Paul Menzel (Code Review)