Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86192?usp=email )
Change subject: tree: Use true false for PcieRpEnable[] ......................................................................
tree: Use true false for PcieRpEnable[]
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528 Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Sean Rhodes sean@starlabs.systems Reviewed-by: Erik van den Bogaert ebogaert@eltan.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/imb-1222/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M util/mainboard/google/puff/template/overridetree.cb 78 files changed, 370 insertions(+), 370 deletions(-)
Approvals: Sean Rhodes: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve build bot (Jenkins): Verified
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1338292..1de7292 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -89,7 +89,7 @@ end device ref pcie_rp3 on # Ethernet controller - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" @@ -98,7 +98,7 @@ end device ref pcie_rp4 on # Wireless controller - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -107,7 +107,7 @@ end device ref pcie_rp9 on # NVMe controller - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 21661f9..996bced 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -251,7 +251,7 @@ # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text) device ref pcie_rp1 on # dGPU; x4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -260,7 +260,7 @@ end device ref pcie_rp7 on # NGFF; x2 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" @@ -269,7 +269,7 @@ end device ref pcie_rp9 on # LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" @@ -278,7 +278,7 @@ end device ref pcie_rp10 on # WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb index c91ffaa..4a01a5a 100644 --- a/src/mainboard/asrock/imb-1222/devicetree.cb +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -209,7 +209,7 @@ }" end device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[7]" = "16" @@ -217,13 +217,13 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[3]" = "4" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpSlotImplemented[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" @@ -231,7 +231,7 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" end device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[6]" = "6" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 2fa7a30..48a2bbc 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -112,7 +112,7 @@ device ref uart2 on end device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -121,7 +121,7 @@ chip drivers/wifi/generic device pci 00.0 on end end - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -129,7 +129,7 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -137,7 +137,7 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index ac4ec46..749cb7c 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -66,7 +66,7 @@ device ref uart2 on end device ref pcie_rp1 on device pci 00.0 on end # x4 TBT - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -76,7 +76,7 @@ end device ref pcie_rp5 on device pci 00.0 on end # x1 LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -84,7 +84,7 @@ end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -93,7 +93,7 @@ end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index d7070fe..64c9760 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -157,7 +157,7 @@ device ref pcie_rp3 on # x1 baseboard WWAN # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "0" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" register "PcieRpLtrEnable[2]" = "1" @@ -167,7 +167,7 @@ device ref pcie_rp6 on # x1 baseboard i210 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "0" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" register "PcieRpLtrEnable[5]" = "1" @@ -177,7 +177,7 @@ device ref pcie_rp9 on # x4 FPGA # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 971d886..3e1ccab 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -193,13 +193,13 @@ }"
# PCIe port 9 for Card Reader - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 9c1cc44..8187868 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -336,7 +336,7 @@ end end # I2C #4 device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -349,7 +349,7 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ed83f86..7424247 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -289,7 +289,7 @@ device ref pcie_rp3 on # LAN, will be swapped to port 1 by FSP # x1 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" @@ -304,7 +304,7 @@ end device ref pcie_rp4 on # x1 WLAN - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" @@ -317,7 +317,7 @@ end device ref pcie_rp5 on # x4 NVMe - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -326,7 +326,7 @@ end device ref pcie_rp9 on # 2nd LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" @@ -339,7 +339,7 @@ end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpClkReqSupport[10]" = "1" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" @@ -347,7 +347,7 @@ register "PcieRpClkSrcNumber[10]" = "2" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpClkReqSupport[11]" = "1" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index f359bf3..421ebc1 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -116,7 +116,7 @@ end device ref pcie_rp7 on # x1 TPU1 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" @@ -125,7 +125,7 @@ end device ref pcie_rp8 on # x1 TPU0 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" @@ -134,20 +134,20 @@ end device ref pcie_rp9 on # x4 i350 LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkSrcNumber[8]" = "2" end device ref pcie_rp10 off - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false" end device ref pcie_rp11 off - register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[10]" = "false" end device ref pcie_rp12 off - register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[11]" = "false" end end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 7ae5255..1de2833 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -78,7 +78,7 @@ device ref uart2 on end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0b4558b..54dc960 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -162,7 +162,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +170,7 @@ register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 3a624d9..09a95df 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -20,7 +20,7 @@ }"
# No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 691e51f..8e7c0b0 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -20,7 +20,7 @@ }"
# Enable Root port 9(x2) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -28,7 +28,7 @@ register "PcieClkSrcClkReq[1]" = "1"
# Enable Root port 11(x2) for NVMe. - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "10" @@ -36,7 +36,7 @@ register "PcieClkSrcClkReq[2]" = "1"
# No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d6f5f60..656cd6b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -20,7 +20,7 @@ }"
# No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false"
# Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 43801bf..27d642d 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -71,14 +71,14 @@ }"
# PCIe port 7 for M.2 E-key WLAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # RP 7 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3"
# Enable Root port 13 (x4) for dGPU - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "12" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index b1df825..bcdcd52 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -20,7 +20,7 @@ }"
# No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false"
# Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index bac387d..45c364b 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -23,7 +23,7 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
# No PCIe WiFi - register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5f81bec..e143327 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -310,7 +310,7 @@ end device ref pcie_rp1 on # WLAN - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 51ba199..4f5e543 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index c93cc4b..d9238b8 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -366,7 +366,7 @@ device ref pcie_rp1 on end device ref pcie_rp4 on # x1 - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -379,7 +379,7 @@ end device ref pcie_rp5 on # x4 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -388,7 +388,7 @@ end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 1187636..b3eabfd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -361,7 +361,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 289cc72..c1c0b20 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -325,7 +325,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" @@ -338,7 +338,7 @@ end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7869dc5..0c40c92 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -314,7 +314,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index f9edf26..676b331 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -305,7 +305,7 @@ end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 724d2ad..199a63c 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -184,10 +184,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 2eee315..6482682 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -162,7 +162,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +170,7 @@ register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 073222b..81fac90 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -173,7 +173,7 @@ }"
# PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index eec6189..2db0b63 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -245,10 +245,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 3bfb9b4..0bd90ee 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -253,10 +253,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 0595df2..ec19352 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -177,45 +177,45 @@ }"
# PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false"
# PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -224,9 +224,9 @@ # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index a3e15c4..88f98ef 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -245,10 +245,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 09a473c..6e6a869 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -177,45 +177,45 @@ }"
# PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[9]" = "false"
# PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -224,9 +224,9 @@ # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 9754826..7e43c2b 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -168,10 +168,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index de0e8a2..859da99 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -178,10 +178,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 4309ec7..7125c40 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -184,47 +184,47 @@ }"
# PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port 9 for SSD (PCIe Lanes 9-12) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10-12 disabled - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false"
# PCIe root port 13 TPU0 - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port 14 TPU1 - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 4 register "PcieClkSrcUsage[4]" = "13" register "PcieClkSrcClkReq[4]" = "4"
- register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 04604c4..df25e86 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -179,10 +179,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d245844..e09e861 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -182,18 +182,18 @@ }"
# PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 569abe5..e0f052f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -182,23 +182,23 @@ }"
# PCIe port 8 for Card Reader - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[3]" = "3"
# PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 304b4d5..049859a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -42,30 +42,30 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "0" - register "PcieRpEnable[17]" = "0" - register "PcieRpEnable[18]" = "0" - register "PcieRpEnable[19]" = "0" - register "PcieRpEnable[20]" = "0" - register "PcieRpEnable[21]" = "0" - register "PcieRpEnable[22]" = "0" - register "PcieRpEnable[23]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "true" + register "PcieRpEnable[10]" = "true" + register "PcieRpEnable[11]" = "true" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" + register "PcieRpEnable[16]" = "false" + register "PcieRpEnable[17]" = "false" + register "PcieRpEnable[18]" = "false" + register "PcieRpEnable[19]" = "false" + register "PcieRpEnable[20]" = "false" + register "PcieRpEnable[21]" = "false" + register "PcieRpEnable[22]" = "false" + register "PcieRpEnable[23]" = "false"
register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index cfccfc9..266c698 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -40,30 +40,30 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "1" - register "PcieRpEnable[17]" = "1" - register "PcieRpEnable[18]" = "1" - register "PcieRpEnable[19]" = "1" - register "PcieRpEnable[20]" = "1" - register "PcieRpEnable[21]" = "1" - register "PcieRpEnable[22]" = "1" - register "PcieRpEnable[23]" = "1" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false" + register "PcieRpEnable[16]" = "true" + register "PcieRpEnable[17]" = "true" + register "PcieRpEnable[18]" = "true" + register "PcieRpEnable[19]" = "true" + register "PcieRpEnable[20]" = "true" + register "PcieRpEnable[21]" = "true" + register "PcieRpEnable[22]" = "true" + register "PcieRpEnable[23]" = "true"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index e49c102..0133a11 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -3,22 +3,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 50bff81..157a465 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -41,22 +41,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 2265d64..8df9851 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -26,22 +26,22 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" + register "PcieRpEnable[0]" = "true" + register "PcieRpEnable[1]" = "true" + register "PcieRpEnable[2]" = "true" + register "PcieRpEnable[3]" = "true" + register "PcieRpEnable[4]" = "true" + register "PcieRpEnable[5]" = "false" + register "PcieRpEnable[6]" = "false" + register "PcieRpEnable[7]" = "false" + register "PcieRpEnable[8]" = "true" + register "PcieRpEnable[9]" = "false" + register "PcieRpEnable[10]" = "false" + register "PcieRpEnable[11]" = "false" + register "PcieRpEnable[12]" = "false" + register "PcieRpEnable[13]" = "false" + register "PcieRpEnable[14]" = "false" + register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 20ea0c1..cd17307 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -75,37 +75,37 @@ end device ref i2c4 off end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" register "PcieRpClkSrcNumber[6]" = "2" end device ref pcie_rp8 on - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" register "PcieRpClkSrcNumber[7]" = "3" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" end device ref pcie_rp14 on - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" register "PcieRpClkSrcNumber[13]" = "5" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" register "PcieRpClkSrcNumber[16]" = "7" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 6bca121..7dae329 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -77,35 +77,35 @@ device ref cio on end device ref pcie_rp1 on # PCIE x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" register "PcieRpClkSrcNumber[0]" = "2" end device ref pcie_rp5 on # PCIE x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on # PCIE x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp9 on # PCIE x1 -> WLAN - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" end device ref pcie_rp10 on # PCIE x1 -> WiGig - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" register "PcieRpClkSrcNumber[9]" = "4" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 29aea40..a030fe7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -124,31 +124,31 @@ }" end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "5" register "PcieRpClkSrcNumber[2]" = "5" end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" register "PcieRpClkSrcNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpClkSrcNumber[8]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index a2d2459..1b8e391 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -148,22 +148,22 @@ device ref pcie_rp1 off end device ref pcie_rp3 on end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "6" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 1a565e5..08eb965 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -210,7 +210,7 @@ end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic @@ -219,7 +219,7 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 74a183b..2aae0d0 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -186,24 +186,24 @@ device ref i2c4 on end device ref pcie_rp1 on end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "0" end device ref pcie_rp8 on # x1 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" end device ref pcie_rp9 on # x4 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpClkReqSupport[12]" = "1" register "PcieRpClkReqNumber[12]" = "1" end diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index f5d05b8..9fb1429 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -86,13 +86,13 @@ }" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 9cf710f..5624d6b 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -22,23 +22,23 @@ end device ref pcie_rp1 on # COMe 4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" end device ref pcie_rp2 on # COMe 5 - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" end device ref pcie_rp3 on # COMe 6 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" end device ref pcie_rp4 on # COMe 7 - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" end device ref pcie_rp12 on # COMe 3 - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" end device ref smbus on chip drivers/i2c/nct7802y diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 3b440a0b..771ea06 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -165,11 +165,11 @@ register "PcieRpClkSrcNumber[9]" = "3" end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpClkSrcNumber[10]" = "3" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[11]" = "true" register "PcieRpClkSrcNumber[11]" = "3" end device ref lpc_espi on diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 6e1ecfd..e097123 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -171,7 +171,7 @@ device ref uart2 hidden end # in ACPI mode device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieRpSlotImplemented[20]" = "1" register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" @@ -180,7 +180,7 @@ end device ref pcie_rp1 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpSlotImplemented[0]" = "1" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" @@ -188,28 +188,28 @@ register "PcieRpAspm[0]" = "AspmDisabled" end device ref pcie_rp5 on # PHY 3 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" device pci 00.0 on smbios_dev_info 3 end end device ref pcie_rp6 on # PHY 4 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" device pci 00.0 on smbios_dev_info 4 end end device ref pcie_rp7 on # PHY 2 - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" device pci 00.0 on smbios_dev_info 2 end end device ref pcie_rp8 on # PHY 1 - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" device pci 00.0 on smbios_dev_info 1 @@ -217,12 +217,12 @@ end device ref pcie_rp9 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp14 on # PHY 0 - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" device pci 00.0 on smbios_dev_info 0 @@ -232,13 +232,13 @@ device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieRpSlotImplemented[14]" = "1" end device ref pcie_rp16 on # M.2 E/CNVi # Disabled when CNVi is present - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 01c5df7..f2c75f3 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -52,14 +52,14 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1"
- register "PcieRpEnable[4]" = "1" # LAN1 - register "PcieRpEnable[5]" = "1" # LAN2 - register "PcieRpEnable[6]" = "1" # LAN3 - register "PcieRpEnable[7]" = "1" # LAN4 - register "PcieRpEnable[8]" = "1" # LAN5 - register "PcieRpEnable[9]" = "1" # LAN6 - register "PcieRpEnable[11]" = "1" # M.2 WiFi - register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 + register "PcieRpEnable[4]" = "true" # LAN1 + register "PcieRpEnable[5]" = "true" # LAN2 + register "PcieRpEnable[6]" = "true" # LAN3 + register "PcieRpEnable[7]" = "true" # LAN4 + register "PcieRpEnable[8]" = "true" # LAN5 + register "PcieRpEnable[9]" = "true" # LAN6 + register "PcieRpEnable[11]" = "true" # M.2 WiFi + register "PcieRpEnable[12]" = "true" # M.2 NVMe x4
# Enable Advanced Error Reporting for RP 5-10, 12, 13 register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index fd20b15..ef1c1a9 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -142,49 +142,49 @@ end device ref pcie_rp1 on # LAN - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpClkSrcNumber[0]" = "0" end device ref pcie_rp2 on # LAN - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" register "PcieRpAdvancedErrorReporting[1]" = "1" register "PcieRpLtrEnable[1]" = "1" register "PcieRpClkSrcNumber[1]" = "1" end device ref pcie_rp3 on # LAN - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "1" register "PcieRpClkSrcNumber[2]" = "2" end device ref pcie_rp4 on # LAN - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" register "PcieRpClkSrcNumber[3]" = "3" end device ref pcie_rp5 on # LAN - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpClkSrcNumber[4]" = "4" end device ref pcie_rp6 on # LAN - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieRpClkSrcNumber[5]" = "5" end device ref pcie_rp9 on # mPCIe WIFI - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index f522e66..9bd8e4f 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -125,7 +125,7 @@ register "SataPortsDevSlp[2]" = "1" end device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpHotPlug[6]" = "1" @@ -135,12 +135,12 @@ end device ref pcie_rp8 on device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -148,7 +148,7 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpSlotImplemented[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index d2f1a83..a043006 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -118,7 +118,7 @@ end device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" @@ -126,13 +126,13 @@ end device ref pcie_rp10 on device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index cf1a8b8..e10e41a 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -210,20 +210,20 @@ end device ref pcie_rp21 on register "PcieRpSlotImplemented[20]" = "1" - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X" end device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieClkSrcUsage[1]" = "0x80" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end device ref pcie_rp9 on # GbE #1 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[14]" = "8" # Type indexes are needed for systemd to use "onboard" names by default @@ -236,12 +236,12 @@ end end device ref pcie_rp10 on # BMC video - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[8]" = "9" end device ref pcie_rp11 on # GbE #2 - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[11]" = "10" device pci 00.0 on diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 18ffb1b..0b912c6 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -144,10 +144,10 @@ }" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" end device ref lpc_espi on # EC/KBC requires continuous mode diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 13ca6e7..00b5ea6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -157,16 +157,16 @@ device ref uart2 on end device ref pcie_rp1 on end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "1" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 3b8343b..851a8bf 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -38,25 +38,25 @@ end device ref pcie_rp5 on device pci 00.0 on end # x1 i219 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieClkSrcUsage[4]" = "0x70" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "0" end device ref pcie_rp6 on device pci 00.0 on end # x1 i210 - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index d8bad2e..c5121f9a 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -81,39 +81,39 @@ end end device ref pcie_rp1 off - register "PcieRpEnable[0]" = "0" # Debug (x1) + register "PcieRpEnable[0]" = "false" # Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" # CORE (x1) + register "PcieRpEnable[4]" = "true" # CORE (x1) register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "1" end device ref pcie_rp6 on device pci 00.0 on end # i210 (x1) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device ref pcie_rp7 on device pci 00.0 on end # VL805 Front Rack/UIB (x1) - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "0" end device ref pcie_rp8 on device pci 00.0 on end # VL805 Back MB (x1) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieClkSrcUsage[0]" = "7" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[7]" = "0" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "1" # NVMe (x4) + register "PcieRpEnable[16]" = "true" # NVMe (x4) register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 8a28ca1..15d217b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -49,34 +49,34 @@ end device ref igpu on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[3]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end device ref pcie_rp9 on # Slot JPCIE1 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 97f995d..14dbb0f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -41,12 +41,12 @@ device ref peg0 on end # unused device ref peg1 on # Slot JPCIE1 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device ref pcie_rp1 on # Slot JPCIE1 - register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[2]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device ref pcie_rp3 on @@ -55,12 +55,12 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 7993383..b53a01f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -44,20 +44,20 @@ end device ref pcie_rp1 on # Slot JPCIE4 - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 @@ -65,7 +65,7 @@ end end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 @@ -73,7 +73,7 @@ end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 1d0dc7f..eec01fb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -45,24 +45,24 @@ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref pcie_rp9 on # Slot JSXB2 - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index f5b7a1f..f951aae 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -98,7 +98,7 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -106,7 +106,7 @@ end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 10 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" register "PcieClkSrcClkReq[10]" = "10" @@ -114,7 +114,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 9 (SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" @@ -122,7 +122,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 5 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[5]" = "13" register "PcieClkSrcClkReq[5]" = "5" @@ -130,7 +130,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 7 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[7]" = "14" register "PcieClkSrcClkReq[7]" = "7" @@ -138,7 +138,7 @@ end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 3a99ab4..afdc264 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -113,21 +113,21 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 14 (SSD2) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieClkSrcUsage[14]" = "16" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 15 (SSD3) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[15]" = "20" register "PcieClkSrcClkReq[15]" = "15" end device ref pcie_rp1 on # PCI Express root port #1 x4, Clock 6 (Thunderbolt) - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "1" register "PcieRpHotPlug[0]" = "1" register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED @@ -135,35 +135,35 @@ end device ref pcie_rp5 on # PCI Express root port #5 x4, Clock 10 (USB 3.2) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[10]" = "4" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 8 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[8]" = "8" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp13 on # PCI Express root port #13 x1, Clock 0 (WLAN) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[0]" = "12" register "PcieClkSrcClkReq[0]" = "0" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 1 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[1]" = "13" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 4 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[4]" = "14" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 36744e9..630d669 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -40,7 +40,7 @@ end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -48,21 +48,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index 9170671..132272d 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -33,7 +33,7 @@ end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -41,21 +41,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index effe280..7d2beab 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -41,7 +41,7 @@ end device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -49,7 +49,7 @@ end device ref pcie_rp8 on device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) - register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -61,7 +61,7 @@ end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -70,7 +70,7 @@ end device ref pcie_rp13 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5760e669..d0a79806 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -96,7 +96,7 @@ device ref uart2 on end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -104,7 +104,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 10 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" @@ -112,7 +112,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 6 (WLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[6]" = "13" register "PcieClkSrcClkReq[6]" = "6" @@ -120,7 +120,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 5 (LAN) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[5]" = "14" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 9251440..291cb45 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -133,7 +133,7 @@ end device ref pcie_rp1 on # Root port #1 x4 (TBT) - register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -143,7 +143,7 @@ end device ref pcie_rp5 on # Root port #5 x1 (LAN) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -152,7 +152,7 @@ end device ref pcie_rp6 on # Root port #6 x1 (WLAN) - register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -161,7 +161,7 @@ end device ref pcie_rp9 on # Root port #9 x4 (NVMe) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index cc3c619..6dd4eb3 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -109,35 +109,35 @@ device ref uart2 on end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 13 (WLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[13]" = "13" register "PcieClkSrcClkReq[13]" = "13" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 14 (GLAN) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[14]" = "14" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 15 (Card Reader) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[15]" = "15" register "PcieClkSrcClkReq[15]" = "15" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7e3ef0c..bb49da9 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -106,7 +106,7 @@ end device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[16]" = "true" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -115,7 +115,7 @@ end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -123,7 +123,7 @@ end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD1) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" @@ -131,7 +131,7 @@ end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 7 (GLAN) - register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[13]" = "true" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[7]" = "13" register "PcieClkSrcClkReq[7]" = "7" @@ -139,7 +139,7 @@ end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 9 (Card Reader) - register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[14]" = "true" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[9]" = "14" register "PcieClkSrcClkReq[9]" = "9" @@ -147,7 +147,7 @@ end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[15]" = "true" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 1c5d720..05f4f02 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -99,7 +99,7 @@ device ref pcie_rp1 on end device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -107,21 +107,21 @@ end device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[12]" = "true" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 6712659..7a6033a 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -183,10 +183,10 @@ }"
# PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6"
-
Elyes Haouas (Code Review)