[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and Clock init support

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email )

Change subject: soc/mediatek/mt8196: Add PLL and Clock init support
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Patch Set 26:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84495/comment/30a5ac1c_abb1987a?usp... :
PS26, Line 7: Clock
clock

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/b22855d3_da165ade?usp... :
PS13, Line 1196: 30
> @[e-mail]  […]

Alternatively, most of the `mtcmos_idx` values are `PM_DUMMY1`. Can we store only the two entries

```
{ CG_VDEC_SOC_GCON_1, PM_VDE_VCORE0 },
{ CG_VDEC_SOC_GCON_1, PM_VDE0 },
```

in the array, to save some space for the `.rodata` section? The complete array can be constructed in runtime in `mmvote_init()`. The same approach could be applied to `vote_cg_mtcmos_table` as well.

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/eeb204c9_36437830?usp... :
PS26, Line 863: (
No need for the extra `()`