Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85496?usp=email )
Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA ......................................................................
soc/intel/xeon_sp/lbg: Add support to hide HDA
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no official bit in the IFD to disable it.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lbg/Makefile.mk A src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h M src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/lbg/include/soc/pmc.h M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/skx/romstage.c 8 files changed, 56 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85496/1
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 25dc4f6..82657f9 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,6 +10,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -107,6 +108,10 @@
/* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); }
uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.mk b/src/soc/intel/xeon_sp/lbg/Makefile.mk index 5dedc83..c855003 100644 --- a/src/soc/intel/xeon_sp/lbg/Makefile.mk +++ b/src/soc/intel/xeon_sp/lbg/Makefile.mk @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += soc_pch.c soc_gpio.c -romstage-y += soc_pmutil.c soc_gpio.c +romstage-y += soc_pmutil.c soc_pch.c soc_gpio.c ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c lockdown.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h new file mode 100644 index 0000000..cfe74e8 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#define HDA_PCS 0x54 +#define HDA_PCS_PS_D3HOT 3 +#define HDA_FNCFG 0x530 + +#endif /* DEVICE_AZALIA_H */ diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h index 8c0b669..d365eb5 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h @@ -6,6 +6,7 @@ #define PID_CSME0 0x90 #define PID_ITSS 0xC4 #define PID_RTC 0xC3 +#define PID_PSF3 0xBC #define PID_DMI 0xEF #define PID_GPIOCOM5 0x11 #define PID_GPIOCOM4 0xAB diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h index 88a9b10..133703a 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h @@ -49,4 +49,7 @@ #define GPE0_DW_SHIFT(x) (4 * (x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 + +#define NST_PG_FDIS1 0x628 +#define NST_FDIS_DSP (1 << 23) #endif diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index 2d87be3..acb1785 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -4,5 +4,6 @@ #define _SOC_SOC_PCH_H_
void pch_lock_dmictl(void); +void pch_disable_hda(void);
#endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 83ed20a..fc7dc8d 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> +#include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pmc.h> #include <console/console.h>
@@ -56,3 +59,26 @@ uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } + +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +#define PSF3_HDA_BASE_ADDRESS 0x1800 + +void pch_disable_hda(void) +{ + /* Ensure memory, io, and bus master are all disabled */ + pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + /* Put controller to D3 */ + pci_or_config32(PCH_DEV_HDA, HDA_PCS, HDA_PCS_PS_D3HOT); + /* Lock and disable everything */ + pci_write_config8(PCH_DEV_HDA, HDA_FNCFG, 0x15); + + /* Disable DSP in PMC */ + pmc_or_mmio32(NST_PG_FDIS1, NST_FDIS_DSP); + /* Hide PCI function */ + pcr_or32(PID_PSF3, PSF3_HDA_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, + PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); + + printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index f66022d..819fcc8 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h> +#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> +#include <soc/pch_pci_devs.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> - #include "chip.h"
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) @@ -24,6 +26,10 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); }
uint8_t get_error_correction_type(const uint8_t RasModesEnabled)
-
Patrick Rudolph (Code Review)