Change in coreboot[master]: soc/amd/cezanne: drop PWRS from GNVS

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50563 )

Change subject: soc/amd/cezanne: drop PWRS from GNVS
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soc/amd/cezanne: drop PWRS from GNVS

A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48f97dd3bbd4b947fe3bc4857216a363 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.

Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) 
Reviewed-by: Kyösti Mälkki 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/cezanne/include/soc/nvs.h
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h
index 7eb6cf6..985798b 100644
--- a/src/soc/amd/cezanne/include/soc/nvs.h
+++ b/src/soc/amd/cezanne/include/soc/nvs.h
@@ -15,7 +15,7 @@
    /* Miscellaneous */
    uint8_t		unused_was_pcnt; /* 0x00 - Processor Count */
    uint8_t		lids; /* 0x01 - LID State */
-	uint8_t		pwrs; /* 0x02 - AC Power State */
+	uint8_t		unused_was_pwrs; /* 0x02 - AC Power State */
    uint32_t	cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
    uint64_t	pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
    uint64_t	gpei; /* 0x0f - 0x16 - GPE Wake Source */